Madhu Agarwal

**** ****** **** *****, *** Jose, CA 95120

Phone: 408-***-****, Email: acx2qr@r.postjobfree.com

Objective: To seek a challenging position in the areas of IC layout design, integration & verification

Summary: Over Seventeen years of experience in custom layout design in leading edge manufacturing technology for Intel Microprocessors, ranging from Pentium, Itanium, 2nd, 3rd and 4thGeneration Core Microprocessors. Responsibilities included design of standard cells, memory circuits, I/O interface, data paths, register files and control logics; RC extraction; schematic to layout verification; static timing; clock generation; and floor planning.

Experience:

Sr. Mask Layout Designer, Intel Corporation, Santa Clara, CA July 1995 – Till Present

Key Accomplishments:

Skills:

oLayout Design: Expert latest technology 14 NM .Expert user of GENESYS, Intel layout editor tool for full chip &fub level custom layout, and Cadence Virtuoso Layout Tool

oVerification: High proficiency in Intel DRC/LVS verification flows.

oDesign Rules: Experience in CMOS deep sub-micron technology design rules (65nm or 14nm )

oLeadership & Team-Work: Provided Genesys Layout tool training to new mask design team at Intel Bangalore Design Center. Training covered various best known methods (BKMs) and resolution of issues, like DRCD, floor planning, critical signal routing etc. Consistently ranked very high for team work & mentorship in 360 feed-backs.

oMultitasking and Result Orientation: Experience with multiple design methodologies as well as tosupport multiple design teams simultaneously.Consistently ranked among the most supportive mask designers by various design teams.

Intel® Hybrid Video Gateway SoC (14nm Process)

oAdded multiple new cells in ‘A’&‘B’ Si steppings and performed manual routing to accommodate these new cells.Worked diligently to fix multiple DRC violations created by these new cell addition, which were all approved for the final tape-in.

oFixed multiple DRCD violations, which were created by speed path changesin the design.

Intel Atom Processor Design (Cherryview, Cougar Mountain & Gemini Lake SOC 14 nm& 12nm)

oWorked on DRC clean up, connectivity & routing analysis at cluster/full-chip level using Cadence ICC&Calibre tool.

oFixed highest priority DRC errors on the critical blocks& performed design verification usingLVS/DRC checks.

oRecognized by peers and management for high quality work and on time delivery of the projects.

Xeon Servers (Broadwell, 14 nm)

Worked on DDR PLL fub. Many iteration of ecos completed. It was the most critical fub related to ecos& connectivity. Fixed timing ecos& fixed critical nets routing . Fixed the power grid .

Done Daily communication with DE in India ( Banglore) related ecos& timing fixing.

Xeon Servers (Ivytown, 22nm)

oWas responsible for layout planning of critical datapathfubs. Responsibilities included block partitioning, block-to-block interface, cell hierarchy, critical signal paths, power bussing, and size estimation.

oPerformed layout verification activities including DRC/LVS/ERC/antenna, and verified that the design meets project methodologies..

oWorked with both circuit designers and layout designers to plan, schedule work and negotiate any necessary layout tradeoffs as needed.

Xeon Servers (Jaketown, 32 nm)

oWorked on the layout design of the first pilot fub in each layout milestones. Implemented 82 engineering change orders, verified their completion and quality

oWorked on some of the most critical datapathfubs, which had very high congestion, and included global drivers. Work resulted in on time closure of LOR2 milestone.

oCreated test layouts for DRC regression by using new design rules at beginning of projects.

Core 2 Duo Processor Design (Penryn, 45nm)

oCreated custom layout for 34 standard cells used in sequential logic. These cells were later used as a template to design more complex cells.

oCreated custom layout for two critical Core 2 Duo data path fubs, including control logic design, clock net shielding, and data routing. Work included parasitic extraction, fixing RV violations and optimizing array areas.

Education:CMOS Layout Design Certification course from IBT Institute.

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