ANJALI SONI

Mobile: +91-702*******

E-Mail: acx09w@r.postjobfree.com

JOB OBJECTIVE

Looking for a challenging career, which demands the best of my professional ability in terms of technical and analytical skills, and helps me in broadening and enhancing my current skills and knowledge.

PROFILE SUMMARY

•B.Tech. (Electronics & Telecommunication) with zeal to make a winning career in VLSI.

•PG Certification in VLSI Design from DKOP Labs Pvt. Ltd, Noida (for duration of 9 months).

•Sound knowledge & interest in Digital Electronics.

•Skilled with ability to analyze and interpret unique problems with a combination of training experience and logical thinking to find the right solutions.

•Adept at maintaining healthy relations by building work culture.

•Sound knowledge in verification tools and methodologies and logic design

EDUCATION

2013 B.E. (ECE) from Ajmer Institute of Tech., Ajmer, RTU, passed with 71.00 %.

2009 12th from Central Girls Sr. Sec. School, Ajmer, RBSE Board, passed with 61.54%.

2007 10th from Saraswati Girls Sr. Sec School, Ajmer, RBSE Board, passed with 64.5 %.

SKILLS

•HDL’s & HVL’s : Verilog & System Verilog

•Scripting Languages : TCL/TK, PERL, SHELL

•Methodology : UVM

•EDA Tools : Xilinx ISE, ModelSim, QuestaSim,Rivera Pro,Libero IDE

•Operating System : Linux and Windows

•Hardware Designing : FPGA

TRAININGS

•PG Certification in VLSI Design from DKOP Labs Pvt. Ltd, Noida (for duration of 6 months): Training in VLSI Design from DKOP Labs, where I gained industrial insight into various technologies & tools like FPGA, Digital Design, Verilog .

•ADVANCED TRAINING: Pursuing design and verification course (QCDVE QSOCS certified design and verification engineering)in VLSI from Qsocs Technologies, Bangalore.

•R.P.S. Power Station, Rawatbhata, Rajasthan (for duration of 45 Days).

•Bharat Sanchar Nigam Limited, Ajmer, Rajasthan (for duration of 30 Days).

PROJECTS :

1.Design and Verification of UART

Platform :Windows/Linux Language : Verilog HDL and UVM Tools : Rivera Pro, Libero

Objective: The project focuses on design and verification of UART with AMBA 3 APB protocol. UART is a serial communication protocol which allows the full duplex communication in serial link, it is an essential to computers and allows them to communicate with low speed peripheral devices, such as the keyboard, the mouse, modems etc.

Design

Analyzed the specifications of UART-APB

Prepared micro-architecture for the same

Designed RTL of each sub modules in Verilog HDL

Direct testing of each sub modules was done.

Combined all the sub modules into a final module

Took the RTL of UART-APB and analyzed its functionality

Verification

Prepared the test plan

Prepared the test bench architecture.

Created the test environment in System Verilog

Methodology used is UVM

2.Design and Verification of Asynchronous FIFO

Platform :Windows/Linux Language : Verilog HDL Tools : Rivera Pro, Libero

Objective: This project focuses on design and verification of Asynchronous FIFO which is used in preventing meta-stable state when a signal crosses clock domain (Clock Domain Crossing). As part of the project Asynchronous FIFO with Width 1 byte and Depth 16 is designed in Verilog HDL and simulated using Rivera Pro and coverage reports are generated.

3.Automatic Traffic Light Director and Controller - (Verilog Project)

Platform :Windows/Linux Language : Verilog HDL Tools : Xilinx,Modelsim

Objective: The aim of the project was to implement an advance real time traffic light controller and director based on density of traffic with provision for emergency vehicles using Verilog HDL for writing source code. Skills used: - FPGA, verilog HDL, Mealy Machine, Sequential Encoding.

ACADEMIC PROJECTS

Title: Water Level Detector – (Minor Project)

Description: The report was about to detect the water level.

Title: SMS Based E-Notice Board – (Major Project)

Description: The report was about to design a SMS driven automatic display board.

WORKSHOP

•Participated in workshop on Robotics.

VOLUNTARY ASSIGNMENT

•Volunteered taught under privileged students.

•Successfully conducted cultural & technical events during school and college.

PERSONAL DETAILS

Date of Birth : 09-Aug-1991

Address : BTM 2-Stage, Banglore-76

Languages Known : English and Hindi

Location Preference : Bangalore

DECLARATION

I hereby declare that all the above details are true and correct to best of my knowledge and belief.

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