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Analog Design, Digital Design, CMOS technology, MEMS, cadence, comsol

Location:
Hyderabad, Telangana, 500066, India
Posted:
October 08, 2016

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RESUME

Shaik. Yezazul nishath, B.Tech, M.Tech

H.No.4, Indira nagar, Bangalore,

acwyx7@r.postjobfree.com

+918884333709

OBJECTIVE

Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible. SKILL SET

EDA Tools : Xilinx ISE, Cadence virtuoso, Cadence NClaunch, Lasi Microwind, DSCH, Comsol multiphysics, TINA TI

Languages : Verilog

Platforms : UNIX, Windows

ACADEMIC PROFILE

Education Board/ University Year CGPA / Percentage M. Tech [VLSI VIT University Chennai 2014 - 2016 8.84 Design] campus

B. Tech [ECE] SWCET, affiliated by 2009 -2013 72.6% JNTU Hyderabad

Intermediate Board of Intermediate 2007 - 2009 88% education A.P

SSC Board of secondary 2007 84.5%

education A.P

PROJECTS

M.Tech Semester projects

1) Title: Design of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop (DPLL)

Abstract: The design and analysis of the digital phase locked loop (DPLL) is carried out in this project. It also demonstrates the feasibility of the DPLL in the various applications. The proposed phase frequency detector (PFD) uses 26 transistors analogous to the conventional PFD which uses 54 transistors. It has been observed that the lock in time of the DPLL is very less. In addition to these, an overview on the designing of the charge pump and loop filter is also discussed. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK1 library of 180 nm technology with supply voltage of 1.8 V

Team Size: 1

2) Title: Design of high frequency PMUT for MEMS applications Abstract: Transducer operating at 10MHz frequency has been designed for high frequency MEMS application, scanning a fingerprint by PMUT comes under high frequency application. Optimized PMUT is designed by choosing correct dimensions and the reduction of cross talk between the transducer elements is also achieved. It is designed in the COMSOL Multiphysics tool. Level shifter is designed for generating high voltage signal to drive MEMS device, it has been designed in TINA TI Team Size: 1

3) Title: Design of 8 bit Multiply and Accumulate (MAC) unit using Wallace Tree and carry look ahead adder in Verilog

Abstract: Most DSP applications such as filters require the MAC unit. It is implemented using fast binary adder and multiplier.

Team Size: 1

4) Title: Numerical Analysis of Vibration based MEMS Piezoelectric Energy Harvester Abstract: The MEMS devices are used almost in every field. Piezoelectric energy harvesters are more preferable than conventional batteries to deliver power to MEMS devices because the conventional batteries have short life span and also occupy larger area. In this project the different piezoelectric materials which gives substantial output voltage when placed on cantilever is compared. The results are simulated using COMSOL Multiphysics tool. The thin layer of piezoelectric material is placed on cantilever. The one end of cantilever is fixed and the heavy proof mass is placed at the free end of cantilever. Team Size: 1

B.Tech Projects

5) Title: Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits

Abstract: For mobile applications designers have to work within a very tight leakage power specification in order to meet product battery life and package cost objectives. In this project to overcome leakage power and reactivation power a “stepwise Vgs MTCMOS” technique and sleep transistor techniques are introduced.

Team Size: 2

6) Title: Wireless Earthquake Alarm System For People security Abstract: The aim of the project is to alert people just before the occurrence of an earthquake. The system is designed using microcontroller 8051 and MEMS, LCD, BUZZER are connected to it. Team Size: 5

PERSONAL STRENGTHS

1. Hard working and good at team work

2. Rapid at learning new things

3. Self motivated and determined

4. Positive attitude

WORK EXPERIENCE

Designation Company name Duration

Project Trainee Cognitive Design Technology, Sep 2015- April 2016 Bangalore

PERSONAL INFORMATION

Date of Birth : Nov. 22, 1992

Nationality : Indian

Gender : Female

Languages Known : English,Hindi, Urdu and Telugu.

Marital Status : Single

DECLARATION:

I hereby declare that all the information provided above are true, complete and correct to the best of my knowledge and belief.

shaik. yezazul nishath

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