Thomas Yeh Phone: 669-***-**** Email: acwy19@r.postjobfree.com

OBJECTIVE

Obtain an Electrical Engineer position where I can maximize my technical skills, building on my academic and work experience as a part of the team.

TECHNICAL SKILLS

C / C++ language, Verilog, SystemVerilog, VHDL, Python, shell script, Perl, TCL.

FPGA, RTOS, OOP, Linux, embedded systems, TCL console, Timing closure, SPI, I2C, TCP/IP.

WORK EXPERIENCE

Software Engineer, Supermicro, 2015-2016.7

Developing SAS3 JBOD firmware by C language on ARM cortex R4 by RTOS.

Programming CPLD by Verilog for integrating of chips and debugging by logic analyzer.

Enhancing application service for storage device on Linux by mixing of C++ and C.

Using shell script on Linux for automatic verification in production line.

Controlling the compile process by Perl script.

ACADEMIC PROJECTS

Quadcopter, SJSU https://youtu.be/PvUbFLxbC-s

Building all systems on ARM cortex M3 by FreeRTOS.

Controlling the quadcopter by PID controller and Kalman filter.

Using interrupt and priority of the task for real-time constrains.

Implementing the design by C language.

Ethernet 802.3 IC Design, SJSU

Implement Physical layer and MII (Media Independent Interface).

Designing Media Access Control (MAC).

Building TCP, UDP, IP, ARP, ICMP and DHCP client module.

Implementing the design by Verilog on Xilinx Spartan 6 FPGA.

Optical Flow IC Design, SJSU https://youtu.be/99wwbAIlv9I

Designing the circuit for parallel processing the algorithm.

Real-time image processing for detecting the direction of object.

Using SOPC NIOS II to verify the hardware design by DMA (Avalon bus).

Implementing the design by Verilog and C language on Altera Cyclone IV FPGA.

MIPS CPU, SJSU

Designing Verification plan for the CPU by SystemVerilog.

Solving data hazard and branch hazard problem.

Increasing speed by pipeline structure.

Implementing the design by Verilog on Altera Cyclone IV FPGA.

Root Mean Square (RMS) Calculator IC Design, SJSU

Designing square root module.

Increasing the speed up to 300 MHz by 64 stage pipeline.

Using FIFO Push/Pull model for syncing the transaction of input and output.

Implementing the design by Verilog.

EDUCATION

San Jose State University, San Jose, CA, 2015

Master of Science, Electrical Engineering GPA 3.5/4.0

Yuan Ze University, Taoyuan, Taiwan, 2011

Bachelor of Science, Electrical Engineering

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