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Engineer Design

Location:
Bengaluru, Karnataka, 560001, India
Salary:
700000
Posted:
October 04, 2016

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K. VENU NAIK

TECHNICAL SKILLS

Electronic Design Packages

INCISIVE,INNOVUS,RC,VIRTUOSO,CONFORMAL,VOLTUS,XILINX, QUESTASIM, MODELSIM,

Programming Languages

VERILOG, SYSTEM-VERILOG, C-PROGRAMING

Microcontrollers / FPGA

FPGA [XILINX SPARTAN 6,SPARTAN 3E]

Familiar Protocols

SPI AND I2C PROTOCOL

Familiar OS

WINDOWS, LINUX-OS

Scripting Languages

TCL

Work Experience

Working at Cadence Design System Inc, Bangalore as Application Engineer (Consultant). Appreciable knowledge in both Analog and Digital domain. Working at Cadence since October 2015 to till date.

Supported 10nm project at Qualcomm for FV (LEC) using Conformal. The job involved in helping the team in debugging on LEC issues.

Have appreciable Knowledge on CPF/UPF.

Delivered 4-day training at NIT, Warangal, and MVSR Engineering College on Complete custom IC flow and ASIC flow.

Delivered 1-day Analog training at DLRL, Hyderabad using IC-616(Virtuoso) from schematic to GDSII

Delivered 2-day training at NIT, Durgapur on complete custom IC flow using

HISIM CMOS and ASIC Flow.

Projects

1. Involved in LEC flow execution of 10nm project at Qualcomm. The job involved in helping the team in debugging on LEC issues like Aborts & Non –Equivalent (Non-Eq)

Tools: Conformal

2. Done Physical Design of DTMF design from Floorplan to Place & route

Tools: Innovus

3. Involved in LEC flow execution of 14nm project at Qualcomm. The job involved in helping the team in debugging on LEC issues like Aborts.

Tools: Conformal.

4. As Application Engineer I supported few customers like Broadcomm, Mediatek & Intel for debugging LEC issues like Mapping & Non-Eq’s using renaming rules

5. As Application Engineer I supported few customers like NXP, Digicomm for debugging issues in Physical Design.

Workshop

Verified PLL schematic using functional verification techniques for the complete transistor level design using Cadence PDK generic 45nm process.

Verified ADC schematic design using Cadence PDK generic 45nm process.

Professional Courses

Completed Professional Development program in VLSI system Design, from Sandeepani School of VLSI Design.

Education

Name of degree

University/Board

Specialization

Pass Out Yr

Aggregate

M.Tech

IIT-BHU Varanasi

DTI

2013

83.80

B.Tech

JNTU Hyderabad

ECE

2010

66.27

Intermediate

Narayana Jr College

MPC

2006

76.80

SSC

Sri Krishnaveni school

2004

80.80

Extra-Curricular Activities

I like to play Cricket, Volley Ball, Tennis and trekking.

Personal Details

Date of Birth : 3rd May, 1988.

Address : House No. 14/ 137/2/1/A-G1, Hyderabad

Email ID : acwwd0@r.postjobfree.com

Mobile No : +91-965*******

Declaration

I do here by declare that all the above statements are true to the best of my knowledge and belief.

Place- Bangalore Signature of the Candidate Date-



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