VINAY PARTHASARATHY

acwpw3@r.postjobfree.com +1-716-***-**** San Jose, CA 95110 vinayp1209

OBJECTIVE

Looking for a Full time starting Dec 2016

EDUCATION

The State University of New York Buffalo, NY GPA: 3.5/4 M.S Electrical Engineering, December 2016

Visvesvaraya Technological University Bangalore, INDIA Aggregate: 77/100 B.E Electronics and Communication Engineering 2013

EMPLOYMENT

Juniper Networks - Verification Intern - Sunnyvale, California May 2016 Current

•Developed TestBench (TB) from scratch for I2C and AMBA AHB protocol using SystemVerilog language and UVM methodology.

•Created UVM generator using Perl to build basic frame work of UVM w.r.t DUT interfaces

•Was involved in Place and Route of HighGig interfaces on Altera Stratix V FPGA

•Currently developing a UVM testbench for LPC protocol using SystemVerilog (SV)

Sonus Networks – System Test Engineer - Bangalore, India Jul 2013 Jul 2015

Worked for 2 years on System Test, Verification and automation.

Defense Research and Development Organization - Intern - Bangalore, India Jan 2013 Jun 2013

Designed a FPGA based dual redundant system and Verified UART and serial communication protocols using basic Verilog testbench

SKILLS

SKILLS: SystemVerilog OOP, Verilog, UVM Methodology, Object-oriented language, HDL, Assertions (SVA), Coverage, RTL Design, IC Layout, ASIC Physical Design, VLSI, DRC, LVS, Digital Circuit Design, Static Timing Analysis, Low Power Design, Place and Route, Validation, Perl, C

PLATFORM: Synopsys VCS, Cadence Virtuoso, Spectre, Xilinx ISE, Quartus, Keil u Vision, Unix, Linux

PROJECTS

Verification of AMBA AHB Lite Slave using UVM

Skills: SystemVerilog, UVM Platform: VCS

•Developed Test Plan from scratch and coded sequences with constrain randomization in addition to the Directed TestCases.

•Verified different types of transfers from AHB slave and achieved 100% code coverage of the design.

Verification of 32 Bit MIPS processor ALU using SystemVerilog

Skills: SystemVerilog, UVM Platform: VCS

•Implemented constrained random verification and achieved 100% Code and Functional coverage with directed TestCases to cover corner cases.

•Implemented TLM FIFO logic to compare the result of DUT and the reference model

Verification of I2C slave and LPC (Currently working) protocol using UVM methodology

Skills: SystemVerilog, UVM Platform: VCS

•Developed TestBench (TB) from scratch for constrained random verification of I2C using SystemVerilog language and UVM methodology.

•Developed a UVM generator using Perl and used to build the basic blocks of I2C and LPC TestBench and sequences replicated Master behavior in our verification environment

Designed A star algorithm using Verilog

Skills: Verilog Platform: Xilinx ISE

•Designed an A star algorithm using FSM and verified using Verilog TB

Design of 64 Bit Memory cell using 7T SRAM Cell for Ultra Low Power Operation

Tool used: Cadence Virtuoso (ASIC Physical Layout Design) Simulation: SPECTRE

•Designed 7T SRAM, sense amplifier, decoder and read/write circuit and used graphical plots to estimate proper timing for triggering of sensing circuit to reduce overall delay.

•Executed the power gating methods by controlling sub threshold current using sleep transistors and observed a 20~30% of reduction in leakage power

•Design verification including DRC, LVS and placement on PAD FRAME

Full custom design of 16 Bit Kogge Stone Adder

Tool used: Cadence Virtuoso (ASIC Physical Layout Design) Simulation: SPECTRE

•Designed the schematic and layout of 16 bit Kogge Stone adder and optimized the layout.

Game of SUDOKU: Implementation using NXP LPC1768 ARM Cortex M3

Skills: Embedded C, Assembly language Platform: Keil μvision 4 Hardware: ARM Cortex M3 (LPC1768)

•Project mainly focuses on interfacing ARM Cortex M3 controller LPC1768 with a LCD, joystick and keyboard through UART to provide the user with appropriate Graphical User Interface to play the game of Sudoku.

FPGA based dual redundant system

Skills: Verilog, Embedded C Tool used: Xilinx ISE Hardware: Spartan 3 FPGA

•Designed a FPGA based dual redundant system using RTL Design on Spartan 3 FPGA.

This module, which was also part of Unmanned Combat Air Vehicle (UCAV – RUSTUM 2) was synthesized and the functionality was verified with simulations on Xilinx ISE simulator.

AWARDS

Rising star award at Sonus Networks for delivering a robust solution in verification Jan 2015

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