Project Design
Resume:
Akshata D
M.Tech Second year
VLSI Design and Testing
B.V.B. College of Engineering and Technology
Hubli, India
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CAREER OBJECTIVE
Seeking a position in an organization where my skills and abilities can be creatively utilized to add value to attain professional growth,while being competent and resourceful.
ACADEMIC RECORDS
M.Tech. 1styear(VLSI Design and Testing)
VTU
B.V.B. College of Engineering and Technology, Hubli, Karnataka, India
Pursuing
Aggregate : 8.76
(CGPA)
2016
B.E. (Electronics and Communication)
VTU
Proudhadevaraya Institute Of Technology, Hospet,Karnataka, India
Aggregate : 72.67%
2011 – 2014
P U C
Karnataka Technical Education Board, Bangalore
RVSR PU Science College
Marlanhalli, Tq : Gangavati
Aggregate : 69.33%
2010
S S L C
Karnataka Technical Education Board, Bangalore
MNM High school
Vidhyagiri.Gangavati
Percentage : 75.37%
2008
TECHNICAL SKILLS
Programming Languages: Verilog, VHDL, C,Java.
Simulation Tools : Xilinx 14.2, Cadence Virtuoso 180nm Technology, Matlab, Modelsim, Riviera Tool.
Software’s/Tools : KeiluVision, Miktex.
Platforms : Windows 7, Windows XP,Windows 8.1,Linux.
Area of Interest : VLSI, Verilog,Image processing, Embedded System .
KEY STRENGTHS
Good communication and Presentation skills.
Good social skills, Leadership quality, Good listener.
Adaptable to any situation, Team member, Motivated.
PROJECTS
Academic Project during B.E:
Title: Robust Railway Crack Detection Scheme (RRCDS)Using LED-LDR Assembly.
Software: Embedded C.
Description: This model consists of GPS module, GSM Modem and LED-LDR based crack detector
assembly. LED will be attached to one side of the rail and the LDR to the opposite side. When the LED light falls on the LDR, the resistance of the LDR gets reduced and the amount of reduction will be approximately proportional to the intensity of the incident light. As a consequence, when light from the LED deviates from its path due to the presence of a crack or a break, a sudden decrease in the resistance value of the LDR ensues. This change in resistance indicates the presence of a crack or some structural defect in the rails.
Academic Project during M.Tech (Mini Project-1):
Title: Low Power and Area Efficient Carry Select Adder.
Software: Xilinx 14.2 ISE simulator.
Description: This project focuses on the Power and area of the Carry Select Adder on Chip in VLSI Design Technology. In Conventional Carry Select Adder Two Ripple Carry Adders are used. Instead of using two Ripple Carry Adder (RCA), one RCA is replaced by the binary to excess convertor (BEC). The number of logic gates which are used in conventional RCA are compared with the BEC and then compared with the Carry Select Adder. The area also reduced by using BEC.
Academic Project during M.Tech (Mini Project-2):
Title: Orthogonal Frequency Division Multiplexing (OFDM) simulation for wireless Communication.
Software: Matlab.
Description: OFDM offers flexibility in adaptation to time varying channel condition by adopting the parameters at each subcarriers accurately. To avoid ISI due to multipath, successive OFDM path, successive OFDM symbols are separated by guard band. This makes the OFDM system resistant to multi-path effect. The adoption of this technique in applications such as digital audio/video broadcast, wireless LAN (802.11a and HiperLAN2), broadband wireless (802.16) and xDSL. OFDM is modulated by using higher bits of QAM.(4 bit,16 bit,64 bit,256 bit) bit error rates are compared using Matlab Simulation.
Academic Project during M.Tech (Mini Project-3):
Title: Optimized Reversible Vedic Multipliers for High Speed Low Power operations.
Software: Xilinx 14.2 ISE simulator.
Description: The reversible Urdhva Tiryakbhayam Vedic Multiplier is one such multiplier which is effective both in terms of speed and power. This paper enhances the performance of the previous design. The Reversible gates such as CNOT gate, Peres gate, Feymann gate, BVPPG gate, HNG gate, NFT gate are used here. The Total Reversible Logic Implementation Cost(TRLIC)is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios,wireless communications.
Academic Project during M.Tech (Major Project-4):
Title: Design and Verification of AMBA 3 AHB Lite Protocol using Verilog HDL and GO2UVM Package.
Software: Riviera simulator.
Description: The proposed design provides the arrangement and utilization of an flexible burst operation. Basically, AHB Lite burst operation is that a series of operation happens regarding the size given and it bears all burst sizes. The size is acting as one of the contributions to the master during the burst operation and after every burst operation, the master or slave will go to the IDLE stage. The AHB Lite configuration contains master and slave blocks without arbitration plan. According to this design one master can access the bus at any one time. Multiplexer and Decoders are used to select the appropriate signals between master and slaves that are built-in in the transfer. The work on AHB-Lite master and slave model are designed and verified by using GO2UVM package on the relevant simulator Riviera.
TRAININGS/INTERNSHIP
Undergone an Aptitude Training Program, SMART Conducted by PDIT, Hospet. This program was held from 22nd January 2013 to 10nd February 2013.
Seeked Internship in CVC Private Limited. Bangalore as ASIC design and Verification Intern.2016.
EXTRA CURRICULAR ACTIVITIES
Participated in National Level competition (Trouble Shooting Event) INSIGNIA 2012 held at SDM, Dharwad.
Participated in Technical Quiz Competition held at PDIT-2014, Hospet.
PERSONEL DETAILS
Date of birth
05May 1992
Gender
Female
Marital Status
Single
Nationality
Indian
Languages
Kannada, Hindi, English & Telugu
Declaration
I hereby declare that the above mentioned information is true to the best of my knowledge and belief.
Date:
Place: Hubli (Akshata D)
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