Design Project

P.Venkataramana

E-mail: ************@*****.***

Alternate e-mail:*******@*****.***

Contact: +919*********

CAREER OBJECTIVE:

To work in an environment where I can apply and enhance my knowledge and skill to serve the firm to the best of my efforts.

EXPERIENCE:

POSITION: Graduate Intern in Synopsys Inc (Jan 2016 - present).

During this period got exposure to industry standard tools and methodologies used in Synopsys, have worked on live projects related to UFS VIP. Some of the tasks and responsibilities include integrate OCP_VIP integration into UVM based test-bench UFS_PVE, written script to run test-cases, VTC regression, debugging errors, Code coverage and etc.

CORE COMPETENCIES:

Good knowledge in Verilog HDL, System Verilog and UVM.

Good working knowledge of C programming and PERL.

Good understanding in fundamentals of Logic design, CMOS design and STA.

Good knowledge on AMBA APB and AHB protocol.

ACADEMIC QUALIFICATIONS:

Qualification

University/Board

Year of passing

Percentage

Institution

M.Tech

(VLSI Design)

V.I.T University, Vellore.

2015

8.52 CGPA

B.Tech

(E.C.E)

JNTU KAKINADA.

2012

77.67%

M.V.G.R College of Engineering, Vizianagaram.

Diploma

(E.C.E)

State Board of Technical Education & Training, Andhra Pradesh

2009

74.78%

Govt. Polytechnic, Narsipatnam.

SSC

Board of secondary education,

Andhra Pradesh.

2006

85.16%

ZP High school, Gollaprolu.

TECHNICAL SKILLS:

Programming Languages : C, Verilog HDL, System Verilog, UVM, PERL and TCL

Assembly Languages : 8086µp and 8051 µc

EDA TOOLS:

Functional Verification Tool : Questasim,VCS,DVEand NC-Sim.

Synthesis : RTL Compiler.

ACADEMIC ACHIEVEMENTS:

Got 1st prize, in HARDWARE EXPO during my UG, conducted by SPACE, MVGRCE.

Received Merit Certificate and Scholarship for academic performance in M.Tech 1stsemister.

PROJETS:

1.Design and functional verification of a Synchronous FIFO

Tools: Questasim

RTL Design: Verilog HDL

Verification: System Verilog HVL

Description: In this project a Synchronous FIFO was designed using Verilog based on given specifications. The Verification environment was build using Systems Verilog, all the test bench components like Driver, Generator, Monitor, Scoreboard, Interface etc were written using System Verilog.

2.Design and functional verification of Dual Port RAM using UVM methodology.

Tools: Questasim

RTL Design: Verilog HDL

Verification Methodology: UVM

Description: In this project a Dual port RAM was designed using Verilog based on given specifications. The Verification environment was build using UVM, all the test bench components like Driver, Generator, Monitor, Scoreboard, Interface etc were written using UVM, and verify the functionality of the design using different test-cases.

3.Design and ASIC implementation of Universal Asynchronous Receiver Transmitter.

Tools: Modelsim (Verilog HDL), RTL Compiler and SOC Encounter.

Description: This project presents the design of UART in transmitter mode and receiver mode. UART is a device that is used to transmit or receive serial data through a pre-defined protocol. A design for UART proposed by lattice semiconductor corporation is achieved and ASIC Synthesis flow is carried out to obtain the GDSII file.

4.Design and implementation of signal generator using AT89S52 micro controller with fixed frequency.

Tools: µC89S52, IC741, DAC0808, Keil uvision3 and CRO.

Description: This project objective is to develop a Signal Generator Which is capable of producing a Sinusoidal, Square, Triangular and Pulse Waveforms of fixed Frequency Using a µC.

Mini projects:

Implemented the UVM based test-bench architecture using PERL script.

Implemented RAL model using PERL script.

Design and FPGA implementation of single precision floating point co-processor.

Design of various Analog circuits in TINA-TI.

PERSONAL PROFILE:

Gender : Male

Date of Birth : 06th July, 1991

Marital Status : Unmarried

Languages Known : English, Telugu

DECLARATION:

I honestly declare that the information furnished above is true to the best of my knowledge.

Date: 31.05.2016

Place: Bangalore (P.V.Ramana)

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