Hong Jo Ahn

503-***-****(cell)

acwjp6@r.postjobfree.com

PURPOSE

Looking for a meaningful CMOS/BJT/BiCMOS analog IC or electrical system design/lead position.

INTRODUCTION

Hong Jo Ahn worked for Intel Corp. as a staff analog design engineer (2003-2016). He delivered various functional blocks for next generation test chips and server products. His interests are various types of high performance analog circuit functional blocks including frequency synthesizers (PLL) for multi-standard wireless systems and high speed IO. He worked on analog/digital circuit designs throughout from 80nm to 10nm technology generations. From 1988 to 1996, he worked for Samsung Electronics, ASIC design center in Suwon, Korea and delivered analog/digital mixed circuit ASIC chips for various consumer products.

He received the M.S. degree in electrical engineering from the Illinois Institute of Technology, Chicago, in 1998 and the Ph.D. degree from Ohio State University, Columbus, in 2003.

SKILLS/KNOWLEDGES/Research Areas of interest.

CMOS/BJT/BiCMOS Analog/Digital integrated circuit design, analysis and verification.

High performance Frequency synthesizer (PLL) for wireless applications.

RF wireless front-end circuit and system back ground.

CDR (Clock and Data Recovery).

High speed IO architecture, TX/RX/EQ functional blocks and implementation.

ADC/DAC data converter background.

DFT arrangement for improving chip test efficiency.

High speed analog circuit layouts in advanced CMOS technologies.

System level design -building board/racks and system spec creation, then customization for IC.

CADENCE, HSPICE, PSPICE, ACTEL FPGA, MENTOR GRAPHICS/QUICKSIM, Analog Work Bench.

Hardware (system, product PCB board) debugging, lab experiments using scopes, JBERT & etc.

WORK EXPERIENCE

Intel (October 2003 – May 2016 Hillsboro, OR) Staff Analog Design Engineer.

10nm server processor group

Working with FCDC (Fort Collins Design Center), executing 10nm PLL AIP works.

14nm server processor group

Delivered high speed view pin driver (up to 4GHz off-chip observation).

Completed 14nm SBPLL design validations and modifications.

Completed PV (Performance Validation) works for multiple PLL blocks.

Worked on CPU speed path debugging and consulted 14nm PLL test results.

High Speed IO Validation chip.

Delivered 4GHz/5GHz LCPLLs & SBPLL for high speed IO (PCIE GEN2/GEN3, & QPI) interface.

RXU design lead.

9.6GT validation chip using EMCP for next generation microprocessors.

On-chip jitter injection using TRNG (True Random Number Generator).

On-chip channel characterization using UNIPHY based TX & RX designs.

Advance Design group.

Sr. Component Design engineer.

IO designs for technology lead vehicles (SRAM test chip- 65nm/45nm/32nm technologies).

VCO design for high speed SRAM tests.

SRAM sleep bias control OPA design.

Involved in SBPLL design and debugging.

Delivered tri-gate, 3D transistor version IO for SRAM test chip.

Delivered die files for SRAM test chips.

Texas Instrument (04/2000 – 09/2000) Intern.

Data converter group: PLL for digital video processing.

Mycris, Columbus, OH (10/1998-12/1998) GRA.

CMOS dual band-gap voltage reference for 10-bit A/D, D/A.

Motorola, Schaumburg, IL (05/1998 – 08/1998, 06/1997 – 12/1997) Intern.

Developing & researching embedded passive components (Government program).

1.8GHz high frequency measurement for dielectric constant / capacitance.

1.8GHz/2.4GHz Duo-band RF VCO layout & analysis using embedded passive components.

Samsung Electronics, ASIC center, Suwon Korea (1988-1996) 01/

ASIC design engineer, design technical manager.

DAT (Digital Audio Tape recorder) Servo LSI.

CAE system manager: SUN, APOLO STATION, MENTOR GRAPHICS O/S & application maintenance.

Analog Integrated Circuit Cell Library – Building Analog Functional Blocks.

NTSC/PAL combined LDP (Laser Disk Player) Spindle servo and TBC (Time Base Correction) LSI.

New Digital TBC LSI for NTSC LDP (Mixed IC).

14.2” TFT (Thin Film Transistor) LCD display controller (Digital IC).

X8 speed CD-ROM sled motor control IC (Linear IC).

800MHz receiver amplifier for GSM (Linear IC).

DVDP (Digital Video Disk Player) RF AMP IC (Cooperation with Prof. B.S. Song, Univ. of IL, Champaign-Urbana).

Hi-End Audio system (Audio amplifier & speaker) consultant.

EDUCATION

Ohio State University, Columbus, OH

Electrical Engineering. The Analog VLSI Lab.

Ph.D.: Frequency synthesizer for multi-standard wireless applications.

IEEE TCAS-II paper reviewer (2000-2002).

Illinois Institute of Technology, Chicago, IL

Electrical Engineering.

M.S.E.E.: 1997.

Sogang University, Seoul, Korea

B.S. Electrical Engineering, January, 1988.

21 REGISTERED PATENTS (Inventor) including two US patents (#5179479, #5278705)

List available upon request.

TEACHING EXPERIENCE (1992-1995)

Samsung Advanced Institute of Technology & Samsung Electronics Design Training Center

Analog IC design course.

BOOK CHAPTER

CH8. "Phase Locked-Loop Technique for Frequency Synthesizers in Modern Communication Systems", HANDBOOK OF RF & WIRELESS TECHNOLOGY, Newnes, October 24, 2003.

ISBN-10: 075*******, ISBN-13: 978-0750676953.

PAPERS PUBLISHED

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr, "A 1.1 GHz 12uA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS Technology with Integrated Leakage Reduction for Mobile Applications," IEEE Journal of Solid-State Circuits (JSCC), vol. 43, no.1, January 2008, pp. 172-179.

F. Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr,, "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-κ Metal-Gate CMOS Technology," International Solid-State Circuit Conference (ISSCC) 2008, pp. 376-377.

Y. Wang, H. Ahn, U. Bhattacharya, T. Coan, F. Hamzaoglu, W. Hafez, C.H, Jan, P. Kolar, S. Kulkarni, J. Lin, Y. Ng, I, Post, L. Wei, Y. Zhang, K, Zhang, M. Bohr, "1.1GHz 12uA/Mb-leakage SRAM design in 65nm ultra-low-power CMOS with integrated leakage reduction for mobile applications," International Solid-State Circuits Conference (ISSCC) 2007, pp. 324.

Hong Jo Ahn, and Ismail, M, "GHz programmable dual-modulus prescaler for multi-standard wireless applications," Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, Volume: 1, 2002, pp. 137 –140.

Y.G Yu, S.W. Choi, D.Y Kim, K.T Park, H.J. Ahn, "Design of CMOS composite transistors with improved operating region, " Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on,

vol. 3, 8-11. Aug. 2002, pp. 1034 –1037

S.-J. Yoo, H. Ahn, M. Hella, and M. Ismail, "The Design of 433MHz Class AB CMOS Power Amplifier", in Proc. of 2000 Southwest Symposium on Mixed Signal Design, Feb. 2000, pp.36-40.

Hong Jo Ahn, "Development of a Time Base Correction and Spindle Servo LSI for NTSC/PAL combined Laser Disk Player", IEEE Korea Council Computer Chapter. May 22. 1993.

HONORS & AWARDS

Illinois Institute of Technology: Outstanding GPA Record (4.0/4.0).

Sogang University: Excellent GPA Records Scholarships 1984 – 1985.

Samsung Scholarship: 1986 – 1987.

Samsung Electronics Co. Ltd.:

R&D incentive for the successful development of world’s first NTSC/PAL combined LDP system.

R&D incentive for the successful development of CD-ROM sled motor controller.

Outstanding Inventors Award.

Texas Instrument fellowship student: 2001 – 2002.

Intel Corporation:

Leadership Award from Platform Validation Engineering Group.

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