Design Test Cases

RAMYA PUROHIT

Email:*****.*********@*****.*** Mobile: 886-***-****/984-***-****

LinkedIn: https://in.linkedin.com/in/ramya-purohit-30654377

CAREER OBJECTIVE

To pursue a challenging career in the field of Semiconductor with constant contribution to an organization that provides challenging work environment and the opportunity for professional growth.

PROFILE SUMMARY

•ASIC Design and Verification Trainee at “Maven Silicon”.

•Pursued certification course in VLSI design and verification.

•Master of Technology in Digital Electronics and Communications [D.E.C.].

SKILLS

ASIC Front-end Design and Verification

Domain

Programming Language

C, C++

HDL

Verilog

HVL

System Verilog

TB Methodology

UVM(Universal Verification Methodology)

Verification

Coverage Driven Verification, Assertion based verification

Methodology

–SVA, Random-Constraint Verification

EDA Tools

Xilinx–ISE, Questasim, Modelsim, Rivera-PRO

Operating Systems

Windows, Linux

Scripting language

PERL, TCL

Personal strengths

Team Management, Debugger, Quick Learner

EMPLOYMENT DETAILS

● Profile: Design and Verification Trainee

Institute: Maven Silicon

Duration: January ’16 – Till the Date

oGood understanding of design specification.

oWrite verification plan through design specification Architected reusable Testbench in UVM.

oVerified the IPs with system Verilog.

oDesign the RTL module using Verilog.

oGenerated Functional, Code and Assertion Coverage.

Good knowledge of the bus protocol and applied in designing and verifying IPs.

EDUCATION

2015: M.Tech (D.E.C) from Srinivas School of Engineering, Mangalore, Karnataka- 80%

2013: B.E. (E.C.E) from Jnana Vikas Institute of Technology, Bangalore, Percentage – 66%

2009: 12th from R.T.E.S PU collage, Ranibennur, Haveri, Percentage: 68.16

2007: 10th from Devika English Medium School, Ranibennur - Percentage: 88.6%

PROJECTS

PCS -Physical Coding Sublayer (Design Using Verilog)

Organization

Maven Silicon

Description

PCS resides at the top of the physical layer (PHY), and provides an interface between the Physical Medium Attachment (PMA) sublayer and the Media Independent Interface (MII). It is responsible for data encoding/decoding, synchronization and many more.

My Role

- Designed RTL using Verilog.

- Verified the design using Host_A (as Transmitter) and Host_B (as Receiver) using linear test-bench using Verilog.

SPI Design Verification (UVM)

Organization

Maven Silicon

Description

An already designed RTL of SPI core is verified using UVM.

Multiple test cases were implemented for all the functional

modes of SPI.

My Role

- Created a verification test plan.

-Created testbench using UVM.

-Implemented multiple test cases in UVM.

!Router Designing and Verification (Verilog and UVM)

Organization

Maven Silicon

Description

A 1X3 Router (capable of routing the data packets to three

different clients form a single source network) was designed,

including a register module that can hold data packets

momentarily, to pass onto three different FIFO memories

along with a Finite State Machine and a Synchronizer that

can manipulate the internal signals to carry out the

necessary task in convenient manner.

My Role

- Design a Router of single server and three clients using

Verilog.

- Verified a Router using UVM by creating a configurable and

reusable testbench.

!Performance Analysis of CMOS Full Adder Circuits and VLSI Design of Multiplier Using Mentor Graphics Tool.

Organization

Srinivas School of Engineering

Description

To achieve a high performance Full Adder and Multiplier in terms of Delay, Area, Power dissipation. The high performed Full adder is used in constructing the Multiplier.

My Role

-Designed the 10 different types of full adder schematic.

-Verified each full adder with respect to their performance in

terms of delay, area, power dissipation.

-High performance full adder is used to construct the multipliers and their performance has been amplified and verified.

PERSONAL DETAILS

Date of Birth:

13th July, 1991

Address:

Bhagyalakshmi PG, Mico Layout, Arkere, Bhannerghatta Road Bangalore

Marital Status:

Single

Languages Known:

English, Kannada and Hindi

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