Design Electrical Engineering

Archit Shah

Beaumont, Texas-***** ****.********@*****.***

https://www.linkedin.com/in/archit-shah-50230988 409-***-**** Education: -

Lamar University, Tx – Electrical Engineering, M.E.S. GPA – 4.0 May, 2016 Charotar institute of technology, Changa- Electronics and Communication Engineering, B.E CGPA 7.44/10 May, 2012 Summery: -

Research experience in CMOS signal integrity and low power design, front end of line process and transistor physics.

Solid understanding of digital IC design, Analog/Mix signal design, digital signal processing and static timing analysis

Knowledgeable in RTL to GDS flow, synthesis, place and route, ASIC front end/back end design. Technical Skills

Work Experience: -

Research Assistant Experience, Lamar University, Texas August 2014 –May 2016 3D Analysis of Self-Heating and Its Impact On the Performance of SOI and Bulk FinFET (Sentaurus TCAD)

Studied nature of phonon scattering to analyze its impact on thermal conductivity and mobility of thin silicon

Created 3D simulation models of SOI and Bulk FinFET in Sentaurus TCAD by using appropriate physical models

Analyzed self-heating phenomena in SOI and Bulk FinFET for different structure and boundary conditions

Observed threshold voltage, on-current and leakage current variations in FinFET at higher temperature Soft-error and Crosstalk Mitigation Using Transmission Gate for 45nm Technology (HSPICE)

Transmission gate with varying gate bias with driver sizing was used for crosstalk and soft error mitigation

Checked Effect of PVTA variation on efficiency of proposed technique

30-40% less area penalty was achieved compare to traditional driver sizing method at the cost of some extra delay penalty Academic projects: -

Design and Analysis of Digital IIR and FIR Filter (MATLAB)

Designed elliptic analog low-pass filter, performed bilinear and spectral transformation to design digital IIR bandpass filter

Designed FIR filter using widowing method, frequency sampling method and optimal equiripple design method.

Analyzed effect of coefficient scaling on the frequency response FIR filters. Design Cache Memory Using FPGA Based Cache Controller (Xilinx ISE)

Designed 8 way set associative cache memory for memory size of 2kb

Modelled cache tag memory, cache data memory, comparator and counter by behavior style of modeling

Designed cache controller on based of spatial locality to generate memory addresses if cache miss occurs Design SDRAM Controller (Xilinx ISE)

Designed wish bone compatible, fully synchronous 16/32 bit SDRAM controller. Also wrote a test bench for verification

Design supports different CAS latency, Auto-refresh operation for SDRAM and four bank architecture for memory. Programming Languages: C, C++

Scripting Languages: Perl (beginner), shell, Tcl

Hardware Description Languages: System Verilog, VHDL Verification Methodology: OVM, UVM

Design and Simulation tools: Hspice, Synopsys TCAD, Matlab, Xilinx ISE, Cadence virtuoso, Multisim, Microwind, VCS, Modelsim, Dsch

Computer skills: Linux, UNIX, Windows, MS office

Related course work: CMOS digital IC design, Topics in VLSI design and testing, low power CMOS design and reliability, digital signal processing, digital image processing, Embedded system, digital communication, Microcontroller and interfacing, Design and Implementation of Low Power and High Speed 8-bit Carry Ripple Adder (Microwind, Dsch)

Designed schematic for 8-bit carry ripple adder in Dsch using pass transistor logic

Used Microwind to design efficient layout of adder with the aim of optimizing power, area and delay

Designed adder gives 30% power saving and 53% less delay compared to adder designed with universal gates Publication: -

Sayil, S., Archit Shah, Md Zaman and Mohammad Islam. 2015 “Soft Error Mitigation using Transmission Gate with varying Gate and Body Bias” IEEE design and test (Volume:Pp, issue 99) http://dx.doi.org.libproxy.lamar.edu/10.1109/MDAT.2015.2499272

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