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Design Engineer

Rochester, Minnesota, United States
October 24, 2016

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*** **** **, ***-*** Email-

Faribault, MN – 55021 Tel - 507-***-****


•7years 3months of experience as PCB Hardware Design Engineer from Engineering specification to prototype release

•Have experience in WCA, FMEA analysis, Custom product continuous engineering.

•Experience with High-speed design methodology, mixed signal design, timing measurements and power train architecture.

•Experience in designing complex boards with FPGAs, DSPs, and Video processors.

•Experience in Signal and Power integrity simulations, LTspice simulation.

•Expertise in Design verification, compliance testing, debugging and documentation.

•Individual team player with experience in working with cross functional team, Vendor interaction and coordination..


Development Tools: Cadence Design entry CIS 16.6, Cadence concept HDL 16.6, Altium 14, Mentor graphics DxDesigner 9.0.

Simulation Tools : Cadence –Sigrity 16.6, Mentor graphics – Hyperlynx 9.0, LTspice.

Interfaces : DDR3, QSPI, SPI, I2C, SGMII, SRIO, ONFI, USB 3.0, UART, CAN, LIN and FlexRay.

Hardware : TI-TDA2X series, TMS320 DSP, MSP430 microcontroller, Intel Cheryl trail, Altera stratix-IV series,

Freescale IMX-50, Marvell Processor, Virtex & Stratix FPGA’s.

Instruments : Tektronix DSA (20G), BERT Scope, VNA, Agilent Infinium scope


Cody VanDerVeen: Manager Sageglass 507-***-****), Jones Rajasaker- Project lead Light 669-***-****)


Hardware Engineer – LnT Technology services (Chennai, India)

SageGlass, (Faribault USA)

Wireless Falcon board:

•Complete design implementation for PV/battery operated pluggable wireless controller board for controlling smartGlass.

•Critical component/architecture selection/trade-off: PSoC chip, power module, battery/PV selection, HB driver selection,, wireless communication module.

•Interfaces: USB-1.0, I2C, CAN, Radio interface.

•Power architecture TOA/design, battery charging/PV MPPT design, PCB stack-up design, layout guidelines.

•Developed SOP for battery shelf storage based on discharge cycle, developed SOP for recharge cycle during storage, transportation.

•Functional test plan documentation for validating proto board, developing test fixture.

•Production release coordination with PCB fabrication/ assembly house.

Custom product continuous engineering, FMEA analysis, Product compliance certification:

•Requirement gathering for specific customer requirement and design implementation.

•Proto development, testing and certification.

•Perform ECO for design changes.

•Compliance certification for all SageGlass product w.r.t different countries.

•EMC failure analysis and solution for certification.

•Identified and implemented safety testing procedure (Routine testing, Hi-pot testing) in Manufacturing facility for factory inspection.

•FMEA analysis for ID circuit board failure @ Manufacturing facility, field installation.

•Developed ESD adaptor board, ROI analysis for ESD adaptor to be used in manufacturing facility, improve product design for better ESD performance. Outsourced portion of work to consulting services. Coordinated work with vendor.

INTEL Corp, offshore (India)

•Complete design cycle implementation for 2.5” and M.2 SSD

•Schematic capture, Stack up material analysis, Layout co-ordination (Floor plan, High speed routing guidelines, Enabling constraints)

•Pre & Post layout - SI simulations for DDR3, PCIe 3.0, NAND ONFI, SATA

•LT-spice simulation for power circuits

•Power integrity simulation (AC & DC ) analysis

•Board bring up and debugging

•Compliance testing for DDR3, PCIe, NAND ONFI, SATA, PCIe 3.0

•Correlation analysis for tools simulations vs bench validation results on verifying the silicon behavior.

•Documentation – SI reports, testing documents for production.

Calsonic Kansei (Onsite: Saitama-Japan, Offshore: Chennai)

•Complete design cycle implementation for AR-HUD using TDA-2X TI processor

•Power Budgeting, Power sequencing, Clock scheme implementation.

•Schematic Drafting- Orcad Capture CIS, Cadvance, defined PCB Stack up, Layout co-ordination (Floor plan, High speed routing guidelines.)

•SI simulations for DDR3 signals, eMMC.

•Power Integrity analysis (DC & AC)

•Board bring up and debugging, functional testing.

•Managed offshore team for BCM board WCA.

UVP reference board for automotive Tri-core processors (Bangalore Infineon)

•Complete design cycle implementation for validating all interfaces in Tri-core series microcontroller from Infineon. Developed reference board and configuration daughter card board.

•Schematic Drafting, critical components selection.

•Defined PCB stack-up, Layout co-ordination (Floor plan, High speed routing guidelines)

•Pre & Post layout SI simulations for DDR3 signals

•Board bring up and debugging, functional testing

•Documentation & reports for SI /PI simulations, Testing

Senior Hardware Engineer – Intergraph. (Hyderabad, India)

DVT for Propak-6 (Calgary NovAtel)

•Developed Test plan for Propak 6 VI generation smart AG GNSS product. (ASICS)

•Performed DVT and documented Test report. (Power sequence, power rail ripple measurement, SPI, I2C, USB-2.0 compliance testing.

Bullet Proof Project Frontend Design (Intergraph Hyderabad)

•Develop common input power protection that could be used as reference design for all the product line from compact priced to sophisticated GNSS product.

•Trade off analysis for different design topologies and validating the same using LTSpice simulation.

•Develop reference design and perform compliance testing against ISO7637-2 pulses.

Member technical Staff – HCLT. (Chennai, India)

Reference board desing for MEMS Sensor (Chennai, India)

•TOA for sensors to be used in Android platform with OMAP35 and IMX51.

•I2C fan-out details analysis for connecting all the sensors to same I2C bus.

•Orcad schematics, PCB constraint document.

•Documentation: HLD, DVT test plan and test report.

STE in GSM Baseband (DLRL, Hyderabad)

•Complete design cycle implementation for STE. (Proto board development, reference board design using TMS320 DSP, Altera IV FPGA, MSP430 processor)

•Requirement gathering, TOA for design architecture by interacting with cross functional teams.

•Defining mechanical size for PCB board with inputs from Mechanical team (2U size)

•Power Budgeting, Power sequencing, Clock scheme implementation.

•Filtering design, EMI/EMC design constraint document for mixed signals (For all ADC, DAC channels to be used for different telecom frequency range)

•SI simulations for DDR2 signals.

•Schematics drafting, PCB constraints document.

•HLD document, DVT test plan, DVT test report that includes SPI, I2C, 1Gb SGMII,SRIO, DDR-2 Interface


B.E. Electrical and Electronics Engineering, –Thiagarajar College of Engineering, ANNA University, Chennai, India 2005-2009

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