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Design Engineer Electrical Engineering

Location:
Tacoma, Washington, United States
Posted:
October 17, 2016

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ADARSH PANIKKAR

acw3hw@r.postjobfree.com 253-***-****

SENIOR DIGITAL DESIGN ENGINEER

Extensive expertise in the full life-cycle silicon development from concept to launch for cutting edge processor and chipset serial IOs. Demonstrates excellent analytical skills creating physical layer architecture and link protocol development. Successfully collaborates with global cross-functional teams, recognized for effective team work. Takes ownership of projects, persistent to drive forward in the face of obstacles. Highly disciplined with great attention to detail and committed to resolving problems to meet user and business objectives. SKI LLS

Computer architecture, ASIC design flow, Logic design, Low power IC design, Custom CMOS circuit design flow, Design for testing/debug, Analog mixed signal validation, Synthesis support, Timing verification, Formal equivalence, Clock Domain crossing, Post silicon validation, Board / tester debug, Oscilloscopes, BERT. Programming Languages: Verilog, C, Assembly for 8086, 80x51, M68000, Python. Software: Synopsys synthesis tool, Spyglass, Cadence Virtuoso analog design environment, Mentor ASICs tools, SPICE, Matlab, MS Office, Altera FPGA. Platforms/Operating Systems: Windows Family, Solaris, Linux, AIX, MSDOS. Hardware: IBM, Sun, HP, Dell, Intel Networking: TCP/IP. PROFESS IONAL EXPER I ENCE

Intel Corporation, DuPont, WA 2001-2016

SENIOR DESIGN ENGINEER

Responsible for architecting, implementing and debugging next generation memory and processor interconnect ASICs for Intel Xeon platforms; analyzed risk of critical business decisions; maintained documentation. Supported design integration, synthesis, STA, and lab bring up.

• Owned PCIE transmit digital physical layer interconnect for Intel Skylake. Repartitioned and architected logic for power reduction and routing. Drove all aspects of validation and physical design.

• Architected and implemented four FSMs on Skylake PCIE physical interconnect pertaining to calibration and power reduction.

• Contributed to link initialization sequence for PCIE interconnect on Intel Skylake.

• Contributed to validation strategy and effort on Intel Skylake. Coded events / assertions. Generated Verilog real number models for several analog blocks.

• Owned Questa CDC, Spyglass, Caliber for Intel Lewisburg integrated system clock module. Drove evaluation, implementation and validation of ECOs that led the way for production worthy A0 Silicon.

• Owned several Mixed signal tests on next generation Intel Memory controller.

• Contributed to analog front end training protocol development and identified mitigation strategies for FBD.

• Owned architecture definition of all digital blocks in FBD physical layer data path for industry’s first Fully Buffered DIMM (FBD) design on Intel 5000 Chip set and Intel 6400/6402 Advanced Memory Buffer.

• Owned CDR unit on multiple generations of memory controllers. Devised changes to the existing algorithm to enhance locking time and robustness in presence of ISI. Updated algorithm was used in several subsequent CDR implementations across Intel.

• Devised Phase interpolator linearity and monotonicity self tests that became basis for high volume screening in several subsequent generations of intel chips.

• Owned all digital FSMs for the interconnect physical layer on Intel Millbrook. FSMs included Icomp, Rcomp, Voltage offset calibration, CDR, TX initialization, TX equalization. ADARSH PANIKKAR

acw3hw@r.postjobfree.com Page 2 of 2

• Won a divisional team award for demonstrating exemplary, cross functional teamwork identifying and resolving issues on core and IO and setting standard for seamless core IO co-development.

• Engaged in board and tester level debug support. Designed functional experiments and experiments for test laser probing and fib platforms to prove failure mechanisms.

• Won a department level recognition award for defining, implementing and enabling observability hooks to dramatically lower debug throughput time on Intel 5400 Northbridge.

• Provided extensive support for test boards, probing, python scripting and board setup for Si bring-up on several Intel platforms.

• As single point of contact for quality and reliability testing on memory interconnect, found common effort buckets that spanned CPU and memory. This led to consolidation of reliability testing for two projects, resulting in 50% reduction in planned effort among two teams.

• Saved millions of dollars for Intel by root-causing one of the most complex bugs in Millbrook memory buffer design that could have caused schedule push and not meet customer launch dates.

• Performed extensive circuit review and used engineering judgement to make recommendations on logic re- architecting and partitioning to achieve reduced power and enhanced speed targets for a highly accelerated stepping of Millbrook2.

• Drove bench characterization of low power features for Millbrook2.

• Won a Divisional Recognition Award for leadership innovation for partnering with Intel Research Lab to architect, implement and validate an 8051 based controller to perform analog compensations. Motorola, Austin, TX 1999-2001

DESIGN ENGINEER Personal Communications Sector

Responsible for design and verification of Wireless ASICs for Motorola mobile phones.

• Designed and verification of an ARM Watch Point module that interfaced to an ARM processor, monitored the ARM instruction pipeline and patched stale lines of code.

• Verification of a multi queue serial peripheral interface. EDUCAT ION

Master of Science in Electrical Engineering, University of Texas at El Paso, El Paso, TX Master’s thesis: Algorithm design for delay driven scheduling of designs into a time-multiplexed FPGA. The algorithm was coded in C and is part of a CAD tool for routing and partitioning in FPGA based emulation systems. Bachelor of Engineering in Electronics and Communication, MS University, Tamil Nadu, India PATENTS ( Published Patents with USPTO)

• Non-integer word size translation through rotation of different buffer alignment channels (07672335)

• Training pattern for a biased clock recovery tracking loop(8098783)

• Interpolator linearity testing system (7009431)

• Training pattern based de-skew mechanism and frame alignment (7500131)

• Various methods and apparatuses for lane to lane deskewing (07466723)

• Interpolator testing system (7043392)

• Delaying lanes in order to align all lanes crossing between two clock domains (07346795)

• Dual clock domain deskew circuit (07656983)



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