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FPGA/ASIC Designer

United States
October 16, 2016

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I am an Electrical Engineer currently seeking a full time position in field of RTL Design, ASIC Design, FPGA Design, Physical Design and Computer Architecture & Verification of the digital systems (Available from January 23, 2017).


oMasters of Science in Electrical Engineering Rochester Institute of Technology, Rochester, NY GPA:3.57/4.0 December 2016.

oBachelors of Technology in Electrical Engineering Veermata Jijabai Technological Institute, India GPA:3.50/4.0 June 2012.


oProgramming Languages: Verilog, VHDL, SystemVerilog, UVM/OVM, Perl, Python, Assembly language, Matlab and C++.

oFull Custom Chip Design: Virtuoso & Pyxis Schematic and Pyxis Layout.

oHDL Design tool: Altera Quartus II, Xilinx Vivado & ISE.

oDRC/LVS tools: Mentor Graphics Calibre.

oSynthesis tool: Leonardo Spectrum, Synopsys Design Compiler.

oSimulators: ModelSim, QuestaSim, Cadence NC Verilog.

oOperating Systems: Windows, Linux/Unix.


Scalable Systems Research Laboratories (ASIC design Intern) June 2016 – July 2016

oSHA-256 Hash Engine (Verilog): Designed an SHA-256 hashing crypto algorithm based on FIPS 180-4 standard using Verilog in Xilinx Vivado design suite. The design was verified using golden test vectors generated by a C++ model. The design worked at 102 MHz.

Rochester Institute of Technology, Rochester, NY

oTeaching Assistant (EEEE120- Digital Systems 1) Aug 2015 – May 2016

Trained students to master Altera Quartus 2 tool and Altera Cyclone IV FPGA board.

Taught practical lab implementation of basic digital systems involving adders, comparators, flip-flops, combinational/sequential circuits, counters and finite state machines.

oGraduate Research Assistant Aug 2015 – May 2016

Research on Reliable Fault Detection Hardware Architecture for lightweight secure cryptographic algorithms SIMON and SPECK for protection against fault attacks.

The proposed schemes are optimized to have low-area and low-power for lightweight applications.

Used time redundancy technique, Re-computing with Rotated Operands (RERO), to protect the inner sub-blocks of these ciphers.

The performance metrics area, delay and throughput had overheads of 30%, 6% & 6% for SIMON and 11%, 4%, 4% for SPECK.

Kalpataru Power Transmission Limited, India Engineer July 2012 - July 2014

Prepared complete and compliant techno-commercial offer to bid for international EPC HV transmission line projects.

Managed vendors to get all the required Bought Out Items to prepare a competitive bid.

Coordinated with Accounts, Purchase and Design departments to obtain finance, pricing and design details for a compliant bid.

Won TL projects in countries like Philippines, Thailand, Zambia and Kenya.



oPipelined RISC processor (Verilog): Designed 14-bit pipelined single core processor (Harvard Architecture) with custom ISA and 4-way Instruction & Data Caches. SIMD instructions support for text processing. Implemented with Verilog using Quartus 2 & ModelSim. Created a Multi-processor System using four of these CPU’s to implement 4x4 matrix multiplication on FPGA DEO-Nano board.

oMultichannel Adaptive Differential PCM Encoder Decoder using TSMC 0.18µm technology (Verilog): Implemented a high level, fixed point, bit exact software modeling, architecture development, and Top Down Design of a core level RTL database of a Multi-Channel ADPCM codec based on ITU standards G.726 and G.711 using Verilog HDL. All modules were designed, synthesized and verified at the RTL and gate level. Two verification strategies were used to verify operation of the modules i.e. directed tests coded in Verilog HDL, as well as test vectors generated by a bit exact software model of the ADPCM algorithm. Final conformance to the standards was verified using official test vectors published by the ITU. Including test structures, the final netlist was 1.2M gates. The design was implemented using Synopsys design compiler, Cadence NC Verilog and Synopsys Prime Time.

oGraduate paper on Secure Cryptographic Ciphers (Verilog): Designed a reliable architecture for lightweight secure cryptographic algorithms SIMON and SPECK using time redundancy techniques. Implemented the design using Xilinx Vivado.

oUSB/PS2 Keyboard Interface (VHDL): Designed a hardware interface for serial data communication with PS/2 keyboards. The data sent by PS2 at 10 kHz was synchronized with FPGA clock running at 100 MHz using dual flop synchronizer. Implemented using Xilinx ISE.

oUART transmission system (VHDL): Designed a UART transmitter and receiver system to communicate between PC (MATLAB) and Spartan 6 FPGA board at 140 MHz using RS-232 communication protocol. A co-processor was designed to perform mathematical operation on data received from PC. A dual-clocked dual-port FIFO component was also designed as a buffer between the receiver & transmitter and the co-processor.

oAssembler for RISC Processor (Python): Developed a Python program to generate an assembler to covert an assembly language code for a Pipelined RISC processor to machine language and create a Memory Initialization File.


oVLSI digital IP core for the Sobel edge detection (VHDL): Schematic & circuit design to detect edges in a 256x256 pixels image. The design worked at 112 MHz clock frequency. Implemented gate level simulation using Mentor Graphics’ Leonardo Spectrum, Pyxis Schematic and QuestaSim. Created physical layout using “Schematic-Driven layout” method in Mentor Graphics’ Pyxis Layout tool on 180nm technology node. Performed DRC and LVS checks to ensure layout’s compliance. Extracted layout’s netlist using Calibre and verified the netlist using test vectors.

oFull Custom Layout of an ALU: Digital circuit design of 1-bit ALU. Designed the ALU layout in Pyxis Layout using schematic as reference. Performed DRC and LVS check. Extracted ALU’s netlist using Calibre. Simulated the extracted netlist to verify the layout.

oMulti-stage CMOS Op-amp: Schematic & circuit design development of a 2-stage Cascode op-amp in Cadence tool. Performed corner analysis of this design to check compliance with the given specification. Created physical layout with Cadence Virtuoso on 45nm technology node. Performed DRC and LVS checks to verify the layout’s compliance with design rules and the schematic.


oSystemVerilog Verification Project: Developed a verification testbench environment written using SystemVerilog for a Result Character Conversion (RCC) block of a DTMF receiver. The environment included a driver, scoreboard and monitor. The SV testbench could count the number of successful detections, compute the expected result to compare it with RCC hardware result and report the coverage. DUT tested for 5000 random vectors with 100 % functional coverage using covergroup.

oPerl Verification Project: Developed a Perl program to generate synthesizable Verilog HDL for a multistage pipeline register (like a parallel word shift register) based specific parameters. The parameters i.e. operand width, number of pipeline stages, optional reset value and output filename are either passed by user at command line or read from an input control file. The generated Verilog HDL file was compiled with NC Verilog and synthesized with Synopsys Design Compiler.

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