Engineer Developer

Steven S. Dettwiler

*** ** ***** ****** *********, Oregon 97006 503-***-**** ***********@*****.***

in www.linkedin.com/in/steven-dettwiler-28740713

Hardware Engineer/Validation Engineer/ Power Delivery / Design

Over 20 years of technical and engineering experience with expertise in power delivery validation, circuit signal quality analysis, debugging and root-cause failure analysis. Skilled in architecture validation, test board design, debugging tools and testing components. Recognized team player and collaborator with strong training, supervisory, problem solving and communication skills.

Areas of Expertise

Power Delivery & Validation Plans Hardware Validation Signal Quality Scope Work/DVM Software Testing

Small Board Design/ Layout Component Qualifications Cadence/Allegro Debugging & Troubleshooting

Customer Training, Service & Support Technical Guidance & Leadership

Technical Skills

Software: Cadence-Allegro 16.6, RSLogix 500 PLC, C programming, Solid Works ver.9 Mechanical Cad, Easy PC Electrical Cad v. 18 Windows®, and MS Office Suite, Assembly using MASM, Pldshell, Basic ICE Proc, HTML.

Equipment/Tools: Chroma Load, VRTT, TEK High Speed Digital oscilloscope, DVM, HP Logic Analyzer, NI-DAQ.

Training: Portland CC: PLC Programming, Intro to C, C programming

Intel University: Server Integration,, x86 architecture with ICE development, Signal Quality I, II, III, Bogatin Signal Integrity I, II, Cadence Concept Schematic Capture, Allegro Layout, Networks I, II.

Professional Experience

INTEL CORPORATION, Hillsboro, Oregon 2011 – 2016

Hardware Engineer/ Applications Engineer

Responsible engineer for power delivery analog validation of tablet designs on Intel architecture.

Lead Validation Engineer to drive the development and implementation of a cost reduction Power Management Integrated Chip (PMIC) tablet design solution.

Created comprehensive tablet power delivery validation test plans and trained support technicians on implementing and utilizing the test methodologies and best practices.

Designed and developed interposer/test hook boards for debugging using Cadence/Allegro CAD tools.

Worked with design vendors, ROHM, Texas Instruments, Dialog to resolve power delivery bugs, baseline standard validation procedures and regression testing of PMIC stepping’s.

Achieved all validation and product launch goals and drove costs reductions for multiple projects.

Provided technical OCP (Open Compute Project) and Cloud networking support to Facebook and Amazon.

INTEL CORPORATION (Kelly Temp Services), Hillsboro, Oregon 2010 – 2011

Hardware Design Engineer, Digital Home Group

Designed small daughter test boards and developed signal quality validations.

Created detailed rework standard documents and instructions for all FFRD (Form Factor Reference Designs) which were distributed companywide.

SUMMIT SEMICONDUCTOR, Hillsboro, Oregon 2009 – 2010

Electrical Validation Engineer

Developed and executed electrical system validation test plans for a wireless speaker technology and product during the initial development and testing phase for a startup company.

INTEL CORPORATION, Hillsboro, Oregon

Validation / Sustaining / Application Engineer, Design Engineering Technician 1990 – 2009

Created design schematics and bill of materials using Cadence design tool.

Debugged and evaluated signal integrity using oscilloscopes, DMM, digital analysis system (DAS), in-circuit emulator (ICE), and software tools to power on new designs and validate areas such as USB, PCIe, Memory, SATA, Audio, and LAN.

Developed and executed validation test plans to ensure signal quality, full functionality, overall product readiness and time-to-market.

Reduced costs $1.56M via in-depth engineering analysis of existing components and bill of material alternatives.

Documented and drove to closure engineering issues and fixes by working with mechanical, BIOS, marketing and design engineers to ensure all issues are resolved before the next fabrication iteration.

Provided marketing and desktop product support to multi-national customers (MNC) DELL, Gateway, Micron PC, Diebold and local / international channel customers.

Created and taught technical classes and showcased demos at Intel Developer Forum and Intel Field Focus Training seminars.

Education

Bachelor of Science in Electronics Engineering Technology OREGON INSTITUTE OF TECHNOLOGY

Completed eight credits towards a Master’s in Electronics Engineering OREGON GRADUATE INSTITUTE

Publications and Awards

-Intel Division Recognition Award for Validation Team Leader of Skull Trail (D5400XS) PC Enthusiast Platform

-Intel Division Recognition Award for driving the next generation Trusted Platform Module version 1.2 – IAMT

-Intel Division Recognition Award for creating the first Intel Desktop Board Accessory Kit AGP Digital Display

-Desktop Board D865GRH with Integrated Security Features Trusted Platform Module - Intel Developer Update Magazine

-Intel Advanced BIOS with Flex Module Technology - Intel Developer Update Magazine

-AGP Digital Display (ADD) Cards - Intel Developer Update Magazine

-Dual Load Switching - Intel Developer Update Magazine

-Keeping Transients and Static in check, Power Supply - Intel Developer Update Magazine

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