Validation Engineer

Clay Hofrock Beaverton, OR *****

****@*******.*** https://www.linkedin.com/in/clayhofrock Home:503-***-****

Work Experience:

Intel – Next Generation Maker Product – Silicon Validation Lead

February 2016 to Current

Leading the System on Chip validation for Next Generation Maker Product

Received Divisional Recognition Award

Created Python and Bash scripts to automate testing of GPIO pins

Created Bash script to run multiple instances of testing software to fully stress the platform

Intel – Broxton – Pre-Silicon and Post-Silicon Validation

January 2014 to January 2016

Validating DFX features for the Reset Virtual Team for Broxton

Created an object orientated Python Script (boot script) that can boot raw parts, by applying fuse overrides, firmware patches and other low level work arounds

The “boot script” has been adopted as a converged tool to be used by many future projects

The “boot script” was accepted as a presentation for Intel’s Design and Test technology Conference

Wrote an inventory tracking python script that was accepted as part of a Demo at DTTC for an RFID based inventory tracking tool

Defined and executed the test cases in Python and EFI scripts for each of the reset DFX features

Wrote a Python script to execute thousands of reset cycles, failures were bucketed into known failures in order to get an accurate count of the failing rate.

Debugged any new failures, and worked with designers to find root cause of the failure

Created several Python scripts to aide in debug gathering system information

Intel – Bay Trail – Post Silicon Debug

February 2012 to December 2013

Debugging System On Chip (SOC) platforms, working with several internal validation teams to reproduce issues they were seeing and quickly debug the problem

Validated Python Debug Tools environment prior to silicon arrival

Setup and trained users on debug tools including Python based debugging tools

During power on of Bay Trail, created a python script from scratch enabled users to make progress on their work and not have to wait for a stable fuse recipe

Setup and ran a 4 Day Training session for participants and lecturers from all over the globe

There were over 200 participants dialed in, and the sessions were recorded for later reference

Intel – Haswell/Nehalem Family – Post Silicon Debug/Debug Tools Engineer

February 2005 to January 2012

Debugging Processor and System issues found by internal validation and external customers

Presented DTTC presentation on Validating Post-Silicon tools in a Pre-Silicon environment

Chaired highly visible Task Forces impacting businesses at the Vice President level

Received two Divisional Recognition Awards for enabling the Nehalem and Tylersburg

Debugged a wide variety of customer issues: BIOS setup issues, PCI-E devices consuming too much power, problems with DMI low power states, and floppy drive performance issues

Main point of contact working with the team that creates our software tools for debugging

Created a validation smoke test for Python based debug tools

Main point of contact for the Intel® QuickPath Interconnect visibility tool

Authored the Intel® QuickPath Interconnect user manual

Defined requirements for Intel® QuickPath Interconnect visualization tool

Collaborated with several teams to gather the requirements for the probing solution

Trained end users on how to use the probing solution

Intel - Arizona – Pre/Post-Silicon Design and Validation Engineer

January 2001 to February 2005

I/O Processor with dual XScale cores, SATA/iSCSI/FibreChannel interface, DDR2 interface, PCI-E

Received two Divisional Recognition Awards for debugging critical issues

Saved a ‘Tier One’ OEM account by organizing a system that enabled multiple sites to work on an essential PCI-E fib edit

Education:

B.S. Electrical Engineering; University of Wyoming

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