PATEL ALPESHKUMAR RAMESHBHAI. Email:acvfvy@r.postjobfree.com

**** ****** **, *** # * Contact no:321-***-****

Fairborn, OH – 45324 https://www.linkedin.com/in/alpeshkumar-patel-a998a358

CAREER OBJECTIVE

To obtain a fulltime position for utilizing my background in VLSI, power electronics and communication.

EDUCATION

Master of Science in Electrical engineering July-2016 Wright State University Dayton, OH

GPA: 3.8/ 4.0

Master of Technology in Communication System Engineering June-2014

Charusat University Gujarat, India

CGPA-9.33/10

Bachelor of Engineering in Electronics & communication June-2011

Gujarat University Gujarat, India

Percentage:70/100

RELEVANT COURSEWORK

RF Power Amplifier Design

VLSI Design, Simulation & Testing

CMOS Mixed Signal IC Design

Digital Circuit Design Using FPGA & CPLD

Data Communication & Networking

Power Electronics & Fundamental

Digital Electronics & Communication

RF & Microwave Communication

Wireless & Optical Communication

Wireless Sensor Networks

Antenna & Wave propagation

Digital Signal Processing

PROFESSIONAL EXPERIENCE

Lecturer in Electronics & communication Department July 2013 – July 2014

R.H.Patel Institute of Technology Kheda, India

Taught the electronics & communications major subjects like to the diploma students.

Worked as a lab tutor for electronics subjects & managed the departmental workload.

Project Intern January 2011-April 2011

Twin Antenna Private Limited Gujarat, India

Designed the microwave components like microwave filter, waveguide, coupler for high frequency application.

Worked on system controller for microwave oven for industrial application. Practiced High Frequency Structure Simulator, MATLAB, OrCAD & other technical software.

WORK EXPERIENCE

Phonathon Caller September 2015-November 2015

Wright State University Dayton, Ohio

Learned communication, Office and marketing skills by taking with Alumni of Wright State University.

Worked on Fund Raising Activity for Rise Shine campaign used for student development.

RELEVANT PROJECTS

Design 8 point FFT for the super-hetrodyne receiver using VHDL & simulated on Virtex 6 FPGA ML605 evaluation platform. April-2016

Implemented FFT on FPGA Virtex 6 ml605 evaluation platform for the analog receiver which has sine wave antenna signal as an input & also detect the maximum binary number corresponding the frequency of the sine wave using VHDL code.

Design & simulated a 4 bit FLASH ADC with highest resolution & maximum clock frequency using CADENSE Virtuoso 6.1.5 tool for higher SFDR. April-2016

Designed a 4 bit ADC with the lowest applied input voltage about 0.1v, clock frequency around 100 to 200 MHz & higher resolution. Designed the required components for the ADC like thermometer to binary converters, open loop regenerative comparator, D-flip flop with the lowest power consumption & higher speed.

8-Bit ALU design with low PDA using TSMC 0.25um Cadence virtuoso tool. December-2015

The 8 bit arithmetic & logic unit designed & simulated using Cadence virtuoso 6.1.5 software with low power delay area product for 8 bit arithmetic & logical operation.

Generator logger June-2011

It was a one type of PIC controller program run using real time clock to measure the energy consumption by a particular devices and gives a plot of how much energy used for particular time.

Internship at Twin Antenna Pvt. Ltd. January-2011

Designed the microwave components like microwave filter, waveguide, coupler. Worked on system controller for microwave oven for industrial application.

Multizone security system December-2010

It’s a security system which can be designed using Atmel8051c microcontroller & load the code for the door, fire or window security in it with others sensors.

TECHNICAL SKILLS

Hardware Description Languages: Verilog, VHDL,RTL coding(VHDL & Verilog)

Programming languages: C(Basic),C++, HTML, Python

Simulator Tools: Xilinx ISE,RTL Compiler, Cadence Virtuoso, Synopsys Tetra Max, Multisim, ModelSim, Saber, PSpice, High Frequency Structure Simulator(HFSS), Cadence Spectre Layout Simulator, OrCAD

Other Technical Skills: MATLAB, Cisco Packet Tracer, Embedded System, MS Office

THESIS TOPIC

Multiband Bandpass Filter Using a Modified Right Triangular Patch Resonator at UWB May-2014

It is a bandpass filter which is worked as Ultra Wide Band frequency range for different application purpose. This filter designed and simulated in High Frequency Structure Simulator (HFSS) software.

Novel Bandpass & Bandstop filter using SIW and CSRR Technology December-2013

By combining the advantage of Substrate Integrated Technology and microstrip component this filter can be used as a bandpass and bandstop for a different frequency & use for satellite communication.

PUBLICATIONS

Multiband Bandpass Filter using a Modified Right Triangular Patch Resonator at UWB, IJERT Journal, ISSN: 2278-0181, Volume 3.Issue 4, April-2014.

Design and Analysis of Bandpass and Bandstop filter based on Defected Ground Structure, IJERT Journal, ISSN: 2278-0181, Volume 3.Issue 5, May-2014.

LEADERSHIP & HONOR:

High Frequency Structure Simulator workshop to design microwave passive components, Gujarat, India April-2014

University Academic Excellent Graduate Student, 2nd rank, Charusat University, Gujarat, India May-2014

Presented research paper based on SIW technology used for Microwave Passive Component design for satellite communication in IEEE conference on behalf of my friend. April-2015

Graduate Student Scholarship, Wright State University August-2015

LANGUAGES: Fluent in English, Hindi, Gujarati.

Contact this candidate