Design Engineering

Kapil Majumder

*** **** ****** *** ****, San Jose, CA- 95126

*****.************@*****.*** 312-***-**** https://www.linkedin.com/in/kmajumder

Summary

-Adept in Circuit Design, RTL synthesis, frontend VLSI with core focus on Digital Design (ASIC) and Computer Architecture. Looking for a full time opportunity with a desire to use my programming, designing, verification skills and grow professionally.

-Skilled in static timing analysis (STA), Delay & cache optimizations, Clock analysis, FPGA flow, FSM Design, Fault Testing.

-Knowledgeable in Functional Verification, SV Assertions, Cache coherency protocols, Dynamic Scheduling, Backend VLSI.

Education

-University of Illinois at Chicago, USA August 2013-May 2015

Master of Science in Electrical and Computer Engineering GPA: 3.50/4.0

-Sardar Patel Institute of Technology (SPIT), University of Mumbai, India August 2009-May 2013 Bachelor of Engineering in Electronics Engineering GPA: 3.55/4.0

Skills

-Programming: Verilog HDL, SystemVerilog, C, C++, HSPICE, Assembly Language, Matlab

-Scripting: Linux Shell, Perl, Python

Experience

-SSR Labs Inc. - ASIC Engineering Intern August 2015 - Present

-Designed the hardware for the peripherals viz. Programmable Interrupt Controller and Timer Counter for a novel IoT (Internet-of-Things) Controller in Verilog using Xilinx Vivado.

-Working on the development of UVM Test benches using SystemVerilog for FIFOs, bus arbitration, bus protocols and interfaces (PCI Express mainly) and verification at System (SoC) level.

Academic Projects January 2013 - May 2015

-Verilog RTL Design/Simulation-Based Verification (Altera Quartus II )

-Designed a 16 bit adder that adds 3 numbers, using a speculative “Design for all cases (DAC)” approach. Achieved 33.3% improvement in propagation delay compared to the ripple carry adder design.

-Designed multiple interacting FSMs with Moore output to determine n-mod-3 of 128-bit numbers using ‘one-hot’ encoding. Achieved minimum clock period of 19 ns (best in the class).

-ATPG based Fault Testing and Simulation (ATALANTA & HOPE Simulator)

-Analyzed k-detectability for all bench files in the ISCAS85 benchmark using a graphical representation.

-Presented a lecture on Fault Simulation Techniques, DFT (Design-For-Testability) Methods like BIST, SCAN chain and Ad-Hoc Techniques. Graded as best Presentation in the class for clarity of concepts and explanations.

-VLSI Based Schematic Design and Layout (Cadence Virtuoso)

-Designed a 4-bit Synchronous ALU from transistor level to block level. Performed DRC and LVS checks along with timing analysis of inverter and sequential blocks.

-Obtained 20% improvement in propagation delay by optimizing the hardware and modifying the layout accordingly.

-Parallel Computing (MPI, C)

-Implemented Parallel matrix multiplication using Cannon’s Method and Strassen’s Algorithm. Canon’s method utilized maximum parallelization hence reducing run time by 11x as compared to Strassen’s for 1024*1024 matrix.

-Implemented Matrix power by leveraging associativity and obtained Determinant by LU (Lower Upper) factorization.

-Approximated a solution to an instance of TSP using the nearest neighbor heuristic on samples obtained from TSPLIB. Solution obtained was 20 % longer than exact solution.

-Cache Replacement Policies and Blocking Matrix Method (SimpleScalar Simulator, C++)

-Modified the access times of caches and pipeline width in Intel Core i7 Architecture to determine the performance bottleneck. 2-way issue achieved minimum cost-CPI product.

-Implemented MRU (Most recently Used) which resulted in 30% higher cache miss rates than LRU.

-Performed matrix multiplication with/without blocking. Blocking method achieved maximum compiler optimization.

-Design, Modeling and Fabrication of Microscale weight Sensor (Tanner EDA L-Edit)

-Designed a micro weight sensor based on capacitive transduction with two mask layers (Poly Si and Gold).

-Incorporated the use of interdigitated capacitors to linearly scale up the change in capacitance.

-The minimum feature size that was obtained was 3 um and the device size was 1106 um x 1106 um.

-Design of a radiation hardened Phase Locked Loop (PLL) (HSPICE, Cosmoscope)

-Designed using a voltage charge pump instead of conventional current charge pumps, at 130 nm process. Design was further scaled down using the Predictive Technology Models (PTM) for both low power and high performance models.

-Published a technical paper in the Proceedings of International Conference on Global Technological Initiatives 2013.

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