Designer Design

MASK LAYOUT DESIGNER Semiconductors (will relocate)

Please contact for job or interview “ONLY” JOB is for me.

Michael Wong Santa Clara, Ca. 95051

acvacv@r.postjobfree.com 415-***-****

Objective: Senior Layout Designer

Experience: 25 + years Full time and contract

TOOLS: Cadence (20 + yrs), Virtuoso XL(10 yrs), Calibre

Verification DRC (RVE) LVS tools (10 years) Assura (LVS)

Place and Route tools (5 years)

LAYOUT Experience: Full custom design TOP to transistor level

(25+ years), Digital layout (15 years), Analog/ RF, PLL and

Cache Level (5 years), IO group Level / ESD Structures (5 years)

Mixed Signal / RF (5 years) 65nm, 40nm, 28nm -14nm/ 1 to 7 GHz speed

QUALCOMM (San Diego, Calif.) Senior designer

Contractor Dec 2014- Sept 2015

Mram / decoders/controllers Cadence- 6. 1 XL ( all tools I.C. Design)

SERDES design Analog ( mixed signal) 2 products / mram and RF ( mixed signal)

14nm (mixed cells)test chip,20nm 28nm . Lead contractor for y decoder, control logic

Global foundries &TSMC

Centric-Tech Cork, Ireland Senior designer/

Contractor Aug.- Sept 2014

Mixed dig/ analog 14nm- 28nm Small test chip. for Global foundries

Lead contractor on test chip.

Avago San Jose, Senior designer/

Contractor April 2014-June 2014

Cadence- 6.1 XL ( all tools I.C. Design) Analog

( mixed signal) 28 nm Place and route. Small test chip.

Support lead contractor on test chip.

Entropic (San Diego, Calif.) Senior designer/

Contractor Oct 2013 – Dec 2013

IC- Silicon tuners (Products) Cadence- 6.1 XL

( all tools I.C. Design) Analog ( mixed signal) 28 nm

Place and route. Small test chip.

QUALCOMM (San Diego, Calif.) Senior designer/

Contractor June 2012- OCT 2013

Mram/decoders/controllers Cadence- 6. 1 XL ( all tools I.C. Design)

Analog ( mixed signal) 2 products / mram and RF ( mixed signal)

18/ 20/ 28 / 45nm. Lead contractor for y decoder, control logic

And bottom logic for mram.

Arasan Chip (San Jose,Ca.) Senior designer/

Contractor March 2012 - June 2012

Analog ( mixed signal) Cadence- 6.1 XL for I.P. Device.

Lead contractor on I.P. Device control logic (part).

Ostendo (Carlsbad, Ca.) Senior designer/ Contractor

Jan 2012 - March 2012

Analog- group (RF/ mixed signal) Cadence- 6.1 XL Assura (lvs)

Place & route. Small test chip.

MAX Linear (Carlsbad, Ca.) Global foundries

Senior designer Contractor Oct – Nov2011

Analog- group (RF/ mixed signal) Cadence- XL Assura (lvs)

Place & route 40nm . Support lead contractor RF/ mixed signal.

Oxford (PA.) Senior designer/ Contractor March 2010- July 2010

Mixed Signal (RF) CMOS - Slice level cells 28nm/40nm.

Support lead contractor RF/ mixed signal.

Qualcomm Senior designer/ Contractor June 2008- 2010

Analog (RF/ mixed signal) (28nm/40nm) high speed – wireless chips

Cadence- XL, Custom - Place & route 28nm/40nm. 3 diff. groups.

NVIDIA Senior designer May 2006- June 2008

Sram decoders / I.O. pads group (38nm/45nm).TSMC /

UMC tech. CMOS design Full time for sram/ I.O. pads

Cadence / Diva (650MHz.high speed) Custom - Place & route

Qualcomm Senior designer/ Contractor July 2005-May 2006

Analog/ Mixed signal / cam row decoders (65nm/45nm) TSMC

Cadence lvs - drc tools Custom - Place & route

SUN Microelectronics Senior designer April 1999-July 2005

Microprocessor: Data Path blocks/ Mega cell blocks

/Standard Lib. cells/ fifo blocks and I.O.'s (8 metal layers)

CMOS design 6 years

Custom - Place & route/ Cadence-Virtuoso/Calibre /

Dracula tools. 4 projects in 5.5 years

Xilinx Senior designer / Contractor Oct.1998- May 1999

SPROM Group 4 meg High-Low voltage/Triple well

Decoder control logic- Jtag blocks/ Shift reg. blocks

Custom design/Cadence-Virtuoso/ Opus / Dracula tools

National Semiconductor Senior designer / Contractor

July 1997- Oct. 1997 AND Dec. 1998- Feb. 1999

Analog/ Wireless Group Amplifier blocks-Clock generato

r /Cadence-OPUS-Dracula tools

S3 Corp. Senior designer / Contractor to Full time May 1997 -Oct. 1998

3D graphic-Multimedia Chip Multiplier block/ 2k-4k Ram block

I.O.'s - Custom layout : place/ route tools -Cadence-OPUS/ Dracula tools

Atmel Corp. Senior designer April 1995- June 1997

EEPROM- Flash (2meg-8meg.) Decoder blocks / Charge pump blocks

I.D.T. (Integrated Device Tech.) Senior designer 1985/ 1995

Microprocessor Group (RISC) 3000-4000 (4 yrs)

CPU/ FIFO chip set; Standard Lib. cell/ Cache decoder/

mux decoder locks/ redesign PAL blocks

"References available upon request"

Answers

US citz., 110K year, call anytime (I am local), was contractor, will work anywhere.

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