PCB design and layout

*** ** ** *** ****: 503-***-****

Hillsboro, OR Home: 503-***-****

*****-**** *****: *********@*******.***

Personal Qualifications

Proficient in digital and analog design as well as PCB layout and mechanical design.

Motivated in analyzing problems and solving technical issues.

Highly accomplished individual and team contributor, as well as team and project leader.

Experienced in being a team-to-team interface and conduit between multiple cooperating originations.

Skilled customer technical interface.

Competent debug of circuit boards to component level.

Proficient in root cause failure analysis of complex logic design.

Extremely competent using Oscilloscopes, Multimeters, Analyzers, and lab power supplies.

Motivated in analyzing problems and solving technical issues.

Self-motivated with the ability to produce quality results in a timely manner.

Strong attention to detail, ability to follow instructions, and capable of multi-tasking.

Skills

PCB design and layout utilizing: PADS 9.5 Logic and Layout, Pulsonix, PCB Artist, ExpressPCB, and PCB123 schematic capture / layout software.

Mechanical design utilizing: TurboCAD Deluxe 21.

Programming utilizing: CodeVisionAVR C for Atmel AVR Microcontroller, C/C++ for the microcontroller environment, RMX using PL/M 86, and ASM 86.

Management experience: Department Manager, Program Manager, Planning Engineer, Systems Integration Engineer.

Competent in the use of mechanical and electronic test equipment as well as tools.

Skilled in circuit and PCB rework including soldering surface mount components to 0603.

Able to read schematics, mechanical drawings, and board layout drawings, understand written instructions, and communicate issues.

Ability to assemble, install, configure PC hardware as well as install software and applications.

Fully versed in the usage of MS Office products.

Proficient in writing test plans based on product, customer requirements as well as regulatory standards.

Capable of setup, test, debug, issue resolution, status and final reports with minimum of supervision.

Experience

Cipher Engineering, LLC: 7/2012 to 7/2014

Partner

Responsible for microcode development, logic design, PCB design and layout, part investigation and cost analysis, fabrication, assembly and test.

Defined multiple microcontroller pinout to function layout for maximum utilization to meet customer requirements.

CAD designs for customer enclosures and mounting hardware.

Cipher Systems, Inc.: 6/2012 to 7/2012

Staff Design Engineer

Responsible for PCB design and layout of customer projects.

Pico Machines, LLC: 10/2008 to 6/2012

Partner

Developed integrated multiple LCD Display Module hardware for simple interface between microcontroller and LCD display.

Developed ASCII character based microcontroller interface application to LCD control library.

Integrated display libraries for multiple LCD controllers and displays for use with display modules.

Worked closely with LCD display vendor on first bring up of their display. This included input to their documents and initialization routine.

Interfaced with both LCD library and compiler vendors to resolve issues between their applications and current hardware and operating systems.

Code development for Atmel AVR ATxmega, ATmega and ATtiny family Microcontrollers.

Intel Corporation: 1/1978 to 7/2007

Compatibility Validation Planning Engineer (9/02 to 7/07)

Program Manager for crucial Intel CPU products.

Planning Engineer for CPU products from first Si to product launch and chipset stepping validations.

Compatibility Validation representative to Si Validation, Board Validation, and Test Development teams. This included inter-state site testing standardization training.

Created tools and templates for expedient plan generation, hardware modeling, and indicator generation.

Compatibility Engineering Lab Manager (6/97 to 9/02)

Responsible for Lab test content, direction, implementation, and throughput improvement.

Wrote development plans, ranking foils, probationary and performance reviews for technicians.

Compatibility Engineering Lab Hardware Interoperability Test Team Supervisor (2/92 to 6/97)

Wrote probationary and performance reviews, interfaced with HR and contractor vendor for hiring.

Responsible for selecting, purchasing, and integrating new third-party hardware and software.

Systems Integration Engineer (1/91 to 2/92)

Conducted failure analyses of thermal issues, resulting in system redesign and customer design win.

Resolved shock failures resulting in modifications to the modular CPU and memory boards.

System Integration Senior Technician (7/89 to 1/91)

Conducted environmental qualifications of desktop and server products.

Designed and built PC-AT bus qualification test load simulator boards.

Speech Systems Senior Technician (11/85 to 7/89)

Implemented RMX OS executing from, and including full bootable hard drive image in, EPROM.

Installed hardware units at customer sites, as well as onsite training of customers.

Component Engineering / Reliability Senior Technician (5/83 to 11/85)

Designed and built component test beds, wrote software test suites using PL/M and ASM.

Implemented first use of component active, multilayer burn-in boards. Responsible for design, layout, and vendor interface of parts and fabrication.

Memory Systems Engineering Technician (5/80 to 5/83)

Responsible for test hardware and software development, documentation, and maintenance.

Wrote test software suites in propriety machine micro-code and ASM.

Memory Systems Test Technician (1/78 to 5/80)

Responsible for debug of memory boards and systems to component level.

Designed and built standalone multi-unit test system for PDP-11/70 memory systems.

Education

Heald Institute of Technology

AA, Electronic Engineering Technology

Contact this candidate