Manager Design

CURRICULUM VITAE

AYUSH GARG

Mobile : +91-981*******,956-***-****

E-mail: *****.****.****@*****.***

OBJECTIVE

Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible.

TECHNICAL SKILLS

Software Skill : C

HDL : Verilog

Platform Worked-on : Windows xp/Vista/7/8, Linux

EDA Tools : Xilinx ISE design suite, Model-Sim, Questa-Sim, NC-Sim

EDUCATION

Qualification

Year

Institution

University/Board

Percentage/ CGPA

M. Tech.

[VLSI Design]

2013-2015

SRM Institute of technologies (Delhi-NCR CAMPUS)

SRM University, Chennai

9.29 [CGPA]

B.Tech

[Electronics & communication ]

2008- 2012

HI-TECH Institute of Engineering & Technology Ghaziabad

Gautam Buddh Technical University, Lucknow, U.P

74.9%

Higher Secondary [12th]

2008

S.V.M Ghaziabad

CBSE

57.2%

High school[10th]

2006

S.V.M Ghaziabad

CBSE

74.4%

QUALIFICATIONS

6-weeks industrial training certificate based at Bharat Electronics ltd (BEL), Ghaziabad and successfully completing the project study of defence “identification of friend and foe”.

6-weeks training certificate on embedded system using 8051 at Ducat Pvt. Ltd., Ghaziabad.

Certification on successfully attend a 3-days workshop on Mat lab by Cetpa InfoTech Pvt. Ltd. Noida.

Certification on successfully attend a 2-days workshop on Circuit Analysis using PSPICE Tools conducted by

Info- semi Technologies, Noida.

WORK EXPERIENCE

Worked in Incise InfoTech Pvt. Ltd, Noida as a VLSI Trainee Engineer (Period: JANUARY 2013 – JUNE 2013)

M.TECH THESIS

Design and implementation of the DDR2/DDR3 SDRAM Compatible Controller (using Verilog)

Our challenge going forward is to continue to increase system performance by narrowing the performance gap between processors and memory. If we compared DDR2 with DDR3 then it is designed to run at lower power, higher memory speeds the signal integrity of the memory module.

Based on a common standard bus interface.

This memory controller maximizes channel bandwidth, more flexible, transplantable and minimizes access latencies through efficient request scheduling.

Intelligent refresh.

Developed a controller FSM.

Simulation on model-sim and Synthesis on Xilinx ISE.

Analysis of power by X-Power Analyser (Xilinx).

INDUSTRIAL PROJECT

Design and implementation of i2c communication-IP

The I C (Inter-Integrated Circuit; generically referred to as "two-wire interface")

This I C interface will create the communication between master and slave devices. The interface will read the command of the master and send corresponding response to the master.

Interface design includes read and write operations and will be able to communicate to master and slave through the I2C.

OTHER PROJECTS

Design of arbiter based on timing and Lottery manager.

Developed a lottery and ticket manager algo based arbiter and implemented on Xilinx ISE design suite and simulated on model-sim.

Design and implementation of FIFO.

Safely pass data from one clock domain.

Developed a synchronous FIFO and implemented on Xilinx ISE design suite and simulated on model-sim and analysis a power.

Monitoring and controlling of green house environment (B-tech Project)

Used an 8051 and PIC microcontroller.

Used several sensors to control a temp., moisture, water level and some other factors.

PERSONAL SKILLS AND STRENGTH

Leadership, Team Player

Good Analytical Skills & tact issue of sensitive Nature

Planned and Analytical Approach

Decision making ability

Interacting preferably with professionals and different cultured peoples.

Declaration

I hereby declare that the above written particulars are true to the best of my knowledge and belief.

Place -Ghaziabad Name- Ayush Garg

Contact this candidate