RESUME

RAM PRASAD J M

Email id: acv4lw@r.postjobfree.com

Bangalore Mobile : 900-***-****

Objective:

Seeking a challenging role in a dynamic workforce that utilizes my creative,

communication and interpersonal skills that offers professional growth. I am capable to meet

the organizational goals and work in line with the company’s vision and values.

Educational Qualification:

R V COLLEGE OF ENGINEERING

Pursuing MTech in VLSI and Embedded systems (2012-14).

Aggregate till 3nd Sem-65%

UNIVERSITY VISVESVARAYA COLLEGE OF ENGINEERING, BANGALORE.

Bachelor of Engineering (Electronics and communication), Bangalore

University (2008-12).

Secured a percentage of 73%

MAHILA SAMAJA P U COLLEGE, KOLAR

II PUC – Department of Pre-University, Bangalore (2007-08).

Secured a percentage of 76%.

MAHILA SAMAJA SCHOOL, KOLAR

SSLC – Karnataka Secondary Education Board (2005-06).

Secured a percentage of 87.56%.

Skill Set:

C program

VHDL

VERILOG

PERL scripting

Static Timing Analysis

DFT

Publications:

Published a Paper in IOSR (International Organization of Scientific Research) journal

under the title “Design and Implementation of Flash ADC for Low Power Applications”

(J45026).

Strengths:

Team work

Problem solving

Creative

Project :

1. Using AM Power to charge Mobile battery Sep 2011 - Jul 2012

Extracting AM(Amplitude Modulation) Power from Radio waves is the Objective of

the project.

The Radio waves contains energy which will be wasted if it is not received after

transmission, so we can use that power to charge our mobile battery by incorporating

this system in mobiles.

2. 4-bit Binary array Multiplier Nov 2012 - Jan 2013

Reducing the delay in a multiplier is the objective of this project.

By using mathematical model to design this multiplier in which number of partial

product addition stages has reduced from n-1 to log2 n. So by this the overall delay of

the multiplier is reduced.

This project is developed in Verilog language.

Tools: Cadence

3. 4-bit Flash ADC (Analog to Digital Converter) Mar 2013 – Jul 2013

Reducing the power consumption is the main objective of this Project.

By reducing the kick back noise in the comparator which reduces the Power

consumed by individual comparator. So that overall power consumed by ADC is

reduced.

The schematic of this circuit is designed in 90nm technology.

Tools: Cadence

4. Data Acquisition System Using Flash ADC Sep 2013 – July 2014

The main objective of this project is to reduce the power consumed by ADC and

DEMUX.

The system is power-optimized by ensuring that each constituent stage always drives

two identically matched differential input pairs. This approach eventually reduces the

power consumption of each stage, thereby leading to overall power saving

This project is designed and implemented in a standard 90nm CMOS process.

Tools: Cadence

Experience:

INTEL Corporation, Bangalore

Intern July 2013 – July 2014

Worked on Oasis tool that automates the synthesis of RTL (Register Transfer Level)

models into gate level circuits.

Worked on Quake tool - Quake is a defect-based fault simulator. It reads in the

simulation model, fault lists, and vectors in order to perform fault simulation.

Mentor Graphics FastScan - Used for pattern generation and simulation.

Personal Details:

: Ram Prasad J M

Name

: 05-04-1990

Date of Birth

Gender : Male

: Single

Marital Status

: Jayaram M

Father’s name

: Manjula K

Mother’s name

: Kannada, English and Hindi

Languages Known

: Indian

Nationality

Declaration:

I hereby declare that the above information is correct to the best of my knowledge.

Place: Bangalore Ram Prasad

Date:

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