Engineering Project

PRADEEP C PRASAD

Phone: +1-520-***-**** Email: ************@*****.*******.***

**,****** ****** ******* *** Jose CA, 95134

PROFESSIONAL SUMMARY

Actively seeking full time opportunities in software development and verification starting from May 2016 EDUCATION

UNIVERSITY OF ARIZONA

Master of Science in Electrical and Computer Engineering August 2014 – May 2016 M.S.RAMAIAH INSTITUTE OF TECHNOLOGY.

Bachelor of Engineering in Telecommunication Engineering August 2009– May 2013

University affiliated: Visvesvaraya Technological University, Belgaum TECHINICAL STRENGTH

Programming Languages:

Proficient: C, C++, Data structures using C and C++, Java.

Familiar: VHDL and Verilog, Basics of Embedded Linux programming, MATLAB, HTML5, SQL, OPEN MP, MPI.

Scripting: Familiar with Shell scripting and Python, Tools: Xilinx, Micro vision IDE – Keil, Wireshark, WinSCP, Putty, Microsoft Visual studio and Code blocks, NetBeans, eclipse. SUBJECTS TAKEN

Computer Aided Logic Design, Computer Architecture, Computer networks, Digital control, Engineering of Computer based Systems Cyber Security, Automatic control Systems, Distributed computing systems, Semiconductor processing. ACADEMIC PROJECTS

Designed a new cache design by comparing the Hierarchies of different levels of caches to that of single level and designing one that meets the advantages of both: The purpose of this project is to analyze different cache hierarchies and to design one that includes the benefits of both multilevel and single-level cache. Simple Scalar was used to run simulations with various cache setups to see the differences in performance as different parameters are changed. Various benchmarks, such as mcf, parser, and applu, will be used to find the main advantages of both single-level cache and multi-level cache. Multiple Biometric Parameter Based Intrusion Detection System: Development of an anomaly based intrusion detection system which continuously uses different biometric features to authenticate the user of the computer/information system: In this project the device drivers of the keyboard were manipulated using C++ and a software was created in such a way that even if a malicious user was to hack into the system by the way he types using the keyboard the software determines whether he or she is the default user or not and locks the system down and notifies the user.

Critical path Calculator and High Level Synthesis Tool: Written in C++ to calculate the critical path using the Depth First search algorithm (DFS) for a given pseudo C code, this tool is highly useful in finding the frequency of operations if the given code is implemented in hardware. The main aim of the project was to develop a high level synthesis tool which can generate Verilog code for the given high level sequential code written in C-like language. Implemented a high level Machine Synthesis tool capable of converting a High Level State Machine.

Force Directed Scheduling Tool: Developing a tool using C++ that can convert a C-like behavioral description into a scheduled high- level statement machine implemented in Verilog.

Developed a DNS server On UBUNTU using BIND software: Built DNS server using scripts in Ubuntu by editing DNS cache and rebinding the DNS server name. This project explains how the DNS cache memory works and methods that can be used to hack a DNS server cache in local server by rebinding.

Designing a GUI for the VTR simulator: Design and development of GUI using Java as the base language for VTR CAD tool that can generate architecture files, configuration files, parse the parameters from output files and show on panel and can run benchmarks with specified architecture file.

Tic Tac Toe: Implemented a tic tac toe game using Java as the base language Simulation and Comparison of the Speed of an Armature controlled DC motor using PID Controller and a Fuzzy Logic Controller in Simulink: The DC motor is modelled and converted as a subsystem in SIMULINK for both the controllers. The simulation and development of the PID controller is implemented w.r.t the mathematical model of a DC motor using trial and error method. The Parameters in the PID are tested with the MATLAB/SIMULINK program.

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