Design Engineering

VISHAL NARKHEDE E-mail: ****************@*****.***

M.Tech in VLSI Design (NITK, Surathkal) Phone: +91-779******* A hardworking & dedicated professional possessing 1 year of industrial experience

ASIC Design Flow

Low Power VLSI Design

Physical Design

Static Timing Analysis

Digital System Design using FPGA

Computer Architecture

WORK EXPERIENCE

National Institute of Technology Karnataka, Surathkal. Dec 2015 – May 2016 Assistant Lecturer

I have taught a course “Elements of Electronics and Communication Engineering” for first year B. Tech students. I have also performed lab duties as teaching assistance in ‘VLSI Design Lab’ and ‘Digital System Design Lab’ for third year and second year B. Tech students. 1. VLSI Design Lab

o Tools used : Ngspice for Circuits Simulation, Magic for Layout and Extraction o Lab Assignments : To learn schematic design, layout, extract, LVS and cell characterization for CMOS inverter, CMOS gates and D-Flip flop. Also create standard cell library of CMOS cells - Two and three input NAND, NOR, AND, OR, AOI for two product of two variables, D-Latch and D-flip flip.

2. Digital System Design Lab

o HDL used : VHDL

o Tools Used : Xilinx Vivado 2015.2

o Board : Xilinx Nexys 4 FPGA board

o Lab Assignments : Design, implement and test Combinational, Sequential and Arithmetic circuits on FPGA boards.

Cypress Semiconductor, Bangalore Jun 2014 – Jun 2015 Applications Engineer

o Worked for Cypress memory (SYNC SRAM, ASYNC SRAM and nvSRAM) and full speed USB controller embedded design products.

o My responsibilities includes schematic reviews, failure analysis for customer boards, reporting and fixing any documentation issues, assisting them for Cypress products and migrating boards design EEPROM to nvSRAM.

o Technical support for the serial protocols such as UART/I2C/SPI and full speed USB. Intel Corporation, Bangalore Aug 2013 – May 2014

Intern

Projects : Design of ASIC block using Structured Datapath Flow for microprocessor core Technology : 14 nm

Role : Block Owner

Operating System : Linux

Responsibilities : Circuits design, Formal Equivalence Verification, Placement and Routing, Static Timing Analysis, power optimization, noise analysis and meeting stringent circuit quality metrics for the design.

Master’s Thesis: Thesis includes following two projects as Part-I and Part-II which were designed by using Structured Datapath Flow (Standard-Cell-Based Design) in 14 nm technology. Part-I: Design of 8 bit three stage pipelined processor using Structured Datapath Design Flow.

Total number of Cells = 537, Total Layout Area = 15.9 x 17.5 (µm)2

All timing paths in design converge to positive setup and hold margin for operating frequency of 2.3 GHz.

34.15 % high threshold voltage Vt cells are used to reduce leakage power depending upon positive setup margin.

The critical path length= 434 ps - Shift operation takes longest time in execution stage which includes barrel shifter followed by ALU which decides maximum operating frequency. Part-II: Design of Logic repeaters for performance and power optimization of client and server core.

Gave me very good understanding about interconnect pipelining for global interconnect in high performance cores. Learnt techniques of striking right balance between performance and power for digital circuits.

Logic Repeaters are designed for operating frequency of 3 GHz.

Total number of Cells = 3192, Total Layout Area = 22000 (µm)2

Design is optimized for dynamic power and leakage power using clock gating and Multi-Vt cells. EDUCATION

National Institute of Technology Karnataka, Surathkal Master of Technology in VLSI Design - CGPA: 8.11 Jun 2012 – Jun 2014 Pimpri Chinchwad College of Engineering, Pune (Pune University) Bachelor of Engineering in Electronics and Tele-communication - Aggregate: 69.08% Jul 2008 – Jun 2012

TECHNICAL SKILLS

Programming

Languages

: VHDL, Verilog, C, Perl

EDA Tool : Cadence-Virtuoso, Ngspice, Magic Layout Editor, Electric schematic and layout editor, Xilinx ISE, Vivado 2015.2, Modelsim, PSoC Designer Intel In-house Tools : Tools used for Semi-Custom Design Flow, Static Timing Analysis, etc Academic & Other Highlights

Secured 1st prize in “Circuit Build It-Up Competition” national level technical event “Dexterity 2K10” at Marathwada Mitra Mandal’s College of Engineering, Pune.

Awarded in Central Sector Scheme of Scholarship by government of India during Sep 2008 - Jun 2011.

Volunteered as a Class Representative in third year of Engineering during year 2010 - 2011.

Coordinated Circuit Designing Competition in national level technical event “Techlligent 2011 and 2012” - Pimpri Chinchwad College of Engineering, Pune. ACADEMIC PROJECTS

Design of 16 bit RISC Processor on FPGA using VHDL on Xilinx FPGA Spartan 3E board

Standard R and I instruction formats are used.

Most of the MIPS instructions are supported like Load, Store, Arithmetic (ADD, ADDi, SUB, SUBi), Logical (AND, OR, XOR, NAND, NOR, NOT), and BRANCH instructions in multiple clock cycles.

Fetch stage has longest clock cycle of 7.123 ns, so maximum frequency of operation is 140.4 MHz

(From Synthesis report).

Implementation of Cordic algorithm to compute sinh(x) and cosh(x) using single cordic element in a sequential manner using VHDL

Implemented using Structural modelling with sub-blocks barrel shifter, ALU, control Unit and LUTs.

Maximum operational Frequency: 107.814MHz (From Synthesis report)

The simulated code was downloaded into Xilinx FPGA Spartan 3E starter kit board and operation was verified using Chipscope.

Design of Configuration Logic Block (CLB) based on XC-4000 series FPGA using Cadence Virtuoso

Each CLB has 4 slices and each slice has three LUT’s (two 4 input and one 3 input LUT).

The CLB has two modes: Configuration mode and Operation mode.

Functionality of one slice is verified by configuring it for 9 input variable Boolean function. E.g. F = {A’B’(C+D)} {J’KLM} + N.

Functionality of CLB is verified by configuring it as 16X8 bit distributed RAM. Implementation of KL algorithm for bi-partitioning of input given graph representing the logic gate circuits using PERL

The goal of KL algorithm is to partition input graph into two disjoint subsets with minimum cut cost.

Data Structure used: Hashes and Arrays.

The input graph is represented as adjacency matrix and output is two different disjoint graphs with minimum cut set.

Further it is also extended for different weighted edges. Bachelor of Engineering Project: Controller Area Network (CAN) Protocol based body temperature and heart beat rate monitoring system using PIC microcontroller.

Compiler used: MikroC (MikroC CAN library is used for PIC18F458 programming)

An MCP2551 type CAN bus transceiver is used to connect the microcontroller to the CAN bus.

Used CAN Bus bit rate: 100Kb/s

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