Meghanath Ramireddy
#** *** ****, *** *****, Arekere Mico Layout, Bangalore 560076
Karnataka, India
Mobile: +91-812******* Email: acuxat@r.postjobfree.com
Career Objective
To work in a globally competitive environment on challenging assignments that shall yield the twin benefits of job satisfaction and a steady-paced professional growth so as to achieve self-realization and contribute to the accomplishment of organizational goals.
Technical Skills
Programming Languages: Verilog,System Verilog
Verification Methodologies: System Verilog, UVM
Protocols: UART
EDA Tools: Xilinx, Riviera-Pro, Mentor Graphics-Questasim
Domain Knowledge: ASIC/FPGA front-end Design, Verifying RTL
Professional Trainings
Maven Silicon Certified Advanced VLSI Design and Verification course
From Maven Silicon VLSI Design and Training Center, Bangalore
Dec 2015 – Apr 2016.
Presently doing Internship at Maven Silicon Softech Pvt Ltd, Bangalore.
Project Experience
Project Title: UART (Universal Asynchronous Receiver Transmitter) IP CORE
Description: The IP Core implements the WISHBONE SOC bus interface for serial communication with modems or external devices. It has 8-bit data bus for compatibility. UART will operate in three different modes - Simplex mode, Full duplex mode and loopback mode. The test bench is written with regression test cases in order to acquire maximum functional coverage.
Key features:
WISHBONE INTERFACE with 8-bit or 32-bit selectable data bus mode
Configurable baud rate generator
Configurable data-width with 5,6,7,8 and 9-bits.
Supports half-duplex, full-duplex and loop-back modes of operation.
Supports line break generation and detection.
Supports 1 and 2 stop bits, parity (even, odd).
Provides receiver FIFO with configurable depth.
Roles and Responsibilities:
Architected the class based verification environment using UVM.
Design verification using UVM Methodology.
Functional coverage.
Tools & Technology:
HDL: Verilog
HVL: System Verilog
EDA Tools: Riviera Pro
Project Title: Router 1x3 RTL Design and Verification
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.
Roles and Responsibilities:
Design Architecture
Implemented RTL using Verilog HDL
Architected the class based verification environment using System Verilog and UVM
Verified the RTL model using System Verilog
Generated functional and code coverage for the RTL Verification
Synthesized the design
Tools & Technology:
HDL: Verilog
HVL: System Verilog
EDA Tools: Riviera Pro and Xilinx ISE
Project Title: Dual port RAM SOC – RTL Design and Verification with UVM
Description: RAM_SOC having size of 4k x 64 and supports simultaneous Read and Write operations. This special type of RAM has two unidirectional data ports - an input port for writing data and an output port for reading data. Each port has its own data and address buses. The write port has a signal called WRITE to allow writing the data, whereas the read port has a signal called READ to enable the data output. Both reading and writing occur on the rising of clock edge.
Roles and Responsibilities:
Implemented the Dual port RAM_SOC using Verilog HDL
Architected the class based Verification Environment using SV and UVM
Tools & Technology:
HDL: Verilog
HVL: System Verilog
EDA Tools: Riviera Pro and Xilinx ISE
Education
Bachelor of Technology in Electronics and Communication Engineering
College - Bheema Institute of Technology and Science, Adoni, AP, India.
University – Jawaharlal Nehru Technological University, Anantapur, AP, India.
Years of study – 2010 to 2014
Percentage – 67.38%
Intermediate in Mathematics, Physics & Chemistry (MPC)
College - Dr. Jyothirmayi junior college, Adoni, A.P.
University – Board of Intermediate Education, AP, India.
Years of study – 2008 to 2010
Percentage – 58.1%
10th Class
College - St.Joseph High School, Adoni, AP, India.
University – Board of Secondary Education, AP, India.
Years of study – 2008
Percentage – 56%
Project as part of Graduation:
Title: Advanced Embedded Security System with Image Capturing and Saving
Objective: Design of effective security alarm system that can monitor the banks or some security places with IR sensors, if any intruder is detected at IR sensor then this system immediately take the picture using camera and stores the picture data in laptop.
Personal Profile
Father’s Name : R.Mysura Reddy(Late)
Mother’s Name : R.lakshmi Devi
Date of birth : 1-May-1993
Sex : Male
Nationality : Indian
Hobbies : Playing cricket, Listening to music
Languages : English, Hindi, Telugu
DECLARATION
I hereby declare that all the details furnished above are true to the best of my knowledge.
Date: 18th May 2016
Place: Bangalore Meghanath.R