Design High School
Resume:
Steven C. Johnson
Home:530-***-****
Cell:530-***-****
Email: acup02@r.postjobfree.com
SUMMARY:
* ***** ** *****’s 3DXPoint Memory Technology development.
Senior Mask Designer with 18+ years experience.
Tools: Cadence Virtuoso/Virtuoso XL/DLS/Calibre/Hercules/.
9 years of digital experience: SRAM, Control, Muxes and std. cells
9 years of analog: voltage regulators, current mirrors, I/O buffers, Op Amps, ESD and Mixed signal.
Excellent experience with UNIX and PC tools and software.
EMPLOYMENT:
Mask Designer (Permanent) Intel, Folsom, CA
June 2011 – April 2016
As a IC Mask Designer, I've been working for the past 3 years developing Intel's 3DXPoint memory technology. I've worked on all major blocks of the chip design both analog and digital with the 14nm process. I have also corresponded and worked with employees of Micron in this joint effort and have made significant strides with the process. Tools used were Cadence Virtuoso 6.1 as well as Calibre verification for LVS and DRC.Process: 14nm
Mask Design Consultant Qualcomm, San Diego, CA
May 2011 – April 2011
Assembled SRAM cells and control logic using Cadence Virtuoso XL Version 6.1 and Calibre Graphics for DRC and LVS verification.
Mask Design Consultant Intel, Folsom, CA
November 2010 – March 2011
Custom assembly and routing of standard cells in the NAND Flash
periphery, cache ROM and ESD components using Virtuoso XL.
DRC and LVS verification checked with Calibre. Devices are both
analog and digital. Process: 21nm
Mask Design Consultant Intel, Chandler, AZ
August 2006 – September 2007
Assembled and routed the chip ring consisting of voltage regulators, level shifter and comparators. Assembled various versions of op-amps, oscillator and current mirrors. Tools used are Cadence Virtuoso and Virtuoso XL. DRC and LVS verified with Hercules. Process: 65nm
Mask Design Consultant Qualcomm, Cary, NC
June 2005 – June 2006
Supported engineer on RAM memory arrays and support logic on the Scorpion project. Used Cadence Virtuoso and Virtuoso XL editor. DRC and LVS verification tools are PDV with a Calibre graphics interface.
Processes: 90nm, 65nm, 45nm
Senior Mask Designer Specialist Sun Microsystems, Burlington MA
October 2000 - October 2003
Senior Mask Design Lead with experience on the Millenium project in
completing 4 large sub-blocks using Virtuoso and Virtuoso XL editor.
Verification tools used were PDV with a Calibre graphics interface.
Process: 90nm
Mask Designer IV Intel Corporation, Folsom CA
January 1997 - September 2000
Led a team of five mask designers in the layout of two chip set I/O
ring designs. This included verification of the full chip and
completing tapeouts. Using Cadence virtuoso/PLE editor with Dracula
and Hercules verification, the chips were taped out on schedule.
Mask Designer III Intel Corporation, Folsom, CA
October 1994 - January 1997
Lead mask designer for the left side of the front side bus on the
Pentium (Klamath) processor with three mask designers supporting on
various buffers and random clock logic.
Design Engineering Technician V Intel Corporation, Folsom, CA
January 1992 - October 1994
Upgraded the design of the adder and carry chain for the DUNIT on
the 486DX II which was the first 100MHz microprocessor. Tools
used were CSE, CLCD (Coarse Level Circuit Debugger).
Design Engineering Technician IV Intel Corporation, Folsom, CA
December 1989 - January 1992
Wrote VHDL code using UNIX vi editor for testing VHDL software routines that represented various state machines written by design engineers.
EDUCATION:
Degree: Associate of Science - Computer Electronics
School: American River College, Sacramento, CA
Degree: Bachelor of Music - Piano
School: California State University, Sacramento
High School: Manteca High School, Manteca, CA
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