Raghuram Chadive

Home: 503-***-****

acuo5a@r.postjobfree.com

Objective:

To obtain a challenging position in Product Development Engineering that will utilize my professional and academic skills

Summary:

Over fifteen years of experience working at Intel in product engineering & high volume manufacturing.

Responsible for ramp of Intel’s client, mobile & server products for Pentium 3,4 & iCore series like

Nehalem, Westmere, Haswell/Broadwell, Skylake/Kabylake family of products.

Well versed with product development life cycle and QA life cycle for microprocessors.

Extensive experience in Enabling 1stsilicon debug paving way for power-on activity on intel processors.

As a Team lead for Class test program team delivered many critical releases in-time as per project schedule.

Extensive work experience with Scrum process using Rally tools. Completed scrum master training.

Hands on experience on generation and validation of test patterns.

Proven record of pre/post silicon debug experience and different test methodology development for HVM.

Hands on experience on automated test equipment: Advantest CMT, Schlumberger S9000KX & ST2000.

Excellent team player with good communication and cross functional team skills.

Good proficiency in PERL and UNIX.

Hands on experience in White box, Functional, smoke, sanity, Retesting and Regression testing.

Good proficiency in debugging complex timing related tester patterns and memory allocations.

Defined tap template methodology and reset pattern architecture.

Mentored recent graduate hires and interns by developing the training material.

Ability to learn and adapt to new technologies.

Skills:

Tester Platforms: Advantest T2000, Schlumberger S9000 KX, Schlumberger ST2, Verigy, Sapphire

Languages and Packages: PERL, SQL, HTML, XML, MS-Office, Python

Operating Systems: LINUX/UNIX, Windows

Applications: LABVIEW, MATLAB, Mathcad, PSPICE.

Tools for Scrum process: Rally.

Publication, Presentations & Awards:

Raghu Chadive, “Enabling per pattern sigmode recipe enabling on NHM/WSM products in HVM”, PSLE

Raghu Chadive, “Automated Pattern Validation using Gift-VT on CMT”, PSLE

Raghu Chadive, Ofer Rubin, “Co-development of Gift-VT based CMT Pattern Validation process”, EMG Divisional Recognition Award

Work Experience:

Sr. Product Development Engineer 2011-present

INTEL Corporation, Hillsboro, OR

Currently working in the Functional Test Content team of MDO PDE group as Sr. Product Development Engineer and specialize in following areas:

Skylake/Kabylake functional content owner

oOwned functional content enabling responsibility for multiple Skylake/Kabylake family products in collaboration with offshore design/product teams.

oResponsible for improving the process for delivering functional test modules for HVM.

oImprove the validation process for improved quality.

Haswell/Broadwell functional content owner

oOwn the functional content delivery for Haswell/Broadwell HVM programs.

oResponsible for the definition, implementation and optimization of class manufacturing flow for functional content to support the product ramp.

oOwn the enabling of DFT for maximum observability for functional content for Haswell HVM programs.

oManage the module releases for HVM test programs in a collaborative software environment.

Test Base Management

oMaintained the test base for Haswell/Broadwell, ensuring necessary fault coverage as well as the toggle coverage to meet the product quality needs.

oDelivered the test content to several different customers like wafer sort, burn-in and Class HVM.

oDebugged several build failures which enabled RTL regression and first toggle measurement to commence.

oDebugging RTL failures on tests ported ported from legacy core products.

Test Vectors generation and validation 2005-2011

Worked in the Test Vectors team of IAG PDE group as Sr. Product Development Engineer with more than 6 years experience and specialize in following areas:

State Equation rules for vector conversion flow development

oDeveloped state equation rules in XML across different tester platforms (CMT, S9K, ST2 and SDB) for different test content enabled in HVM test programs for several Intel dual, quad and six core based products

oWorked with designers and trace generation team members to request changes/enhancements in design and traces to support hooks for special debug requirements in HVM

o Wrote test cases and ran regressions to guarantee high quality state equation rules for vector conversion flows for multiple products

oImplemented complex State Equation rules to achieve significant HVM test time reduction for some test content across multiple products.

Signature mode (scanout) test methodology

oEstablished Signature mode test methodologies for several quad and six core based desktop, mobile and Server products

oDefined HVM test program flows and established debug data collection flows to enable Signature mode enabled patterns for increased coverage and higher quality as measured by defects per million on multiple products in HVM.

oDeveloped tool for collecting pattern sigmode health data and generating per pattern reports.

o Expertise in pattern debug by pulling and analyzing high volume data using SQL based scripts and root causing many HVM related yield, down binning and cold socket elimination issues.

oDebugged and root caused many complex timing related tester pattern and trace issues for several products.

Pattern Robustness flow

oDeveloped pattern robustness flow on Configurable Modular Tester (CMT) for dual and quad core based desktop, server and mobile products.

oMigrated and established pattern robustness flow from Schlumberger S9000 KX tester to CMT tester after benchmarking different debug tools available on CMT tester for dual core products.

oValidated tester patterns on CMT & ST2 testers using a debug tool and customized test program.

oDebugged and fixed issues with failing patterns and uploaded pass/fail tags of each pattern to a database.

oEnhanced pattern robustness methodology on iCore product to address the pattern dependency issues.

oDeveloped Pattern debug process to find the issues inside the test.

oUsed Lean methodology for optimizing the whole process for tester and engineer resources.

Reset file management for all vector conversion

oDeveloped tap template methodology on Pentium 4 products to generate the reset files for different HVM content execution and for different tester configurations.

oDefined the reset pattern architecture across multiple tester configurations for first generation of iCore which includes power-up sequence with turning the PLLs on and enabling of the correct DFT features per content.

oEnsured that the reset architecture meets vector memory constraints and is well within test time budget.

oDefining and implementing tester specific training constraints for the high speed cards and integrating tester bit-lock and byte-lock features into the pattern architecture.

oAutomation of reset-init pattern files generation.

oProvided excellent customer support for all content owners and debug teams.

oUsed Lean methodology for optimizing the generation, validation for different testers, product steppings and HVM releases.

Production Suite build and release to HVM

oBuilt and released several production suites for all test content enabled in HVM test programs for Intel dual core based products

o Involved grouping patterns into different pattern list blocks after using a custom tool to enable proper usage by the production test program flows

oWas actively involved in providing first silicon pattern support for different steppings of Pentium Dual Core Desktop/Server processor

CACHE Scrum Master

oCurrently running the cross-functional CACHE scrum as scrum master

oEnforcing scrum rules and practices are followed by all scrum members correctly

oEnsuring the scrum team is fully functional and productive by running the planning, review and retrospective meetings and daily stand up meetings regularly

oConsistently work on the organizational systems to remove impediments for the scrum team and address renegotiation of scope when changes occur in a sprint

oVery good pointer to my people management skills and leadership capabilities

Test Program Expert 2000-2004

Worked in the Test program team of STTD group as Test program Lead with more than 4 years of experience and specialize in following areas:

Test Program Lead

oSuccessfully performed as class test program team lead to support first generation Pentium 4 products.

oImplemented the feed forward system at class programs for decision making across different test sockets.

oEnhanced the test program build/validate/release processes using scrum processes.

oOther achievements include improving the test program compile time 18X by benchmarking against different assemblers, validation of ASAP tools like timing tool, check-time tool, pattern tool and many APIs provided by Schlumberger.

oOwned test programs for Pentium 3 products and supported many ATM sites in Costarica, Cavite, Penang including mentoring factory PEs at these sites.

Class HVM Program I/O Expert for Pentium 4 products

oOwned implementation of I/O spec testing in Class Program.

oDeveloped process of developing timings for HVM programs

oResponsible for studying I/O design specifications, developing vectors, timings, levels for I/O tests.

oDeveloped AC timings generation and validation for 133MHz and 200MHz to support 533MTS and 800MTS using AVM mode on S9K testers.

oDeveloped VIX/VOX testing using the boundary scan patterns and drove its implementation for HVM.

Education:

Western Michigan University at Kalamazoo

Master of Science in Electrical Engineering July 2000

Osmania University, India

Bachelor of Engineering in Electronics and Communication July 1997

Relevant Courses:

PERL, Advantest T2000 Basic Apps, Advantest T2000 Hardware Apps, Schlumberger S9000 and ST2 Pattern anatomy, Advantest T2000 Pattern Anatomy, Scrum Master Training, Lean Methodology, Digital Test Fundamentals, Design for Testability, VHDL, VLSI System Design, Computer Organization and Architecture, Logic System Design

References: Available upon request

US Permanent Resident

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