Naveen java Fresher

Naveen R.

E-mail: acun3g@r.postjobfree.com Contact No.: +91-916*******

Current Location: Bengaluru

Objective

To achieve high career growth through continuous learning process, keep myself dynamic, visionary and competitive with the changing scenario of technology.

TECHNICAL SKILLS

Processors and Controllers:

FPGA VIRTEX-4, Artix-7

FPGA Prototyping:

Xilinx 14.4

Language & Programming:

Verilog

Hardware Design & Analysis Tools:

H- Spice, Cadence – Virtuoso64, NC Sim, SOC Encounter

Other programming languages:

SQL, Core JAVA, J2EE, HTML, CSS

Professional Qualification

Oracle SQL:

-Implementing Database design using Oracle 10G (Query,Retrieve DB, Functions And Joins, Sub Queries, Table Creation, Database Maintain, Indexes, Views, Transaction)

JAVA fundamentals and Programming Language:

-Concept and features of OOP, variables, arrays

-Encapsulation, inheritance and polymorphism

-Implement error handling techniques using exception handling, threads

JDBC:

-Knowledge on designing various applications

ACADEMIC PROJECTS

Title: Design, development and Implementation of RC4 Pseudo random stream generator

Description: The project involves design, code development in verilog and synthesis of RC4 Pseudo Random Stream generator. Results were observed for correctness as the random sequence was generated.

Title: Design, development and verification of I2C master slave Protocol using verilog

Description: This project involves design, development of HDL code and verification of designed I2C master slave protocol using module level-file I/O based test-bench and iterative loop based test benches.

Title: Design and Implementation of Improved Architecture of QPSK modulator in FPGA

Description:

Quadrature Phase Shift Keying (QPSK) is a modulation technique that has been widely adopted in today’s modern wireless communication systems.. The designed architecture was compared with few existing architectures and better optimization was obtained with higher frequency of operation.

EXTRA-CURRICULAR ACTIVITIES

Actively participated in various Workshops and seminars held by National instruments, Mentor Graphics, Synopsys and MatLab at different locations

Interested in farming, Floriculture, cookery, Cricket, Volley ball, listening to Music

Have participated in university level badminton tournaments

EDUCATIONAL PROFILE

M.Sc[Engg] in VLSI system design from M.S. Ramaiah School of Advanced Studies (Affiliated to Coventry University U.K) with aggregate of 58%

Under Graduation in Telecommunication engineering in 2013 from Vivekananda Institute of Technology affiliated to VTU Belgaum with aggregate of 56%

Pre-university from Seshadripuram pre-university main college 2008 with aggregate of 54%

Completed SSLC from M.E.S Kishora Kendra in 2006 with aggregate of 70.24%

PERSONAL PROFILE

Name : Naveen R.

Father’s Name : C. Ramaiah

Qualification : B.E, M.Sc. Engineering (VLSI system design)

Languages Known : Kannada, English and Hindi

Address : #1944/41 2nd main M.C Layout Vijayanagar

Bengaluru – 560040

Mobile : +91-916*******

Email Id : acun3g@r.postjobfree.com

Declaration:

I hereby declare that the information furnished above is true to the best of my knowledge.

Date: Your’s faithfully,

Place: Bengaluru (Naveen R.)

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