Lincy L. Thomas

Email id: acujh0@r.postjobfree.com Mob No: +91-954*******

Career Objective

To work with an educational institution with a challenging role where I can put my skills and knowledge effectively into practice contributing to the organizational and departmental short term and long term goals and thus helping myself to scale new heights in career.

Educational Qualification

M.Tech in VLSI Design and Embedded Systems, College of Engineering Munnar, Cochin University of Science and Technology(2013-2015)(First class with distinction)

PG Diploma in VLSI and Embedded hardware design, National Institute of Electronics and Information Technology (NIELIT), Calicut (Aug 2012- Jan 2013)

B.E-Electronics and communication Engineering – St. Xavier’s catholic College of Engineering, Anna University Chennai (2008-2012) – 7.2 (CGPA)

XIIth – N S S Higher Secondary School, changanacherry, Kerala Higher Secondary Board (2008) – 79%(Distinction)

Xth - St. Josephs Higher Secondary School, changanacherry, Kerala State Board

(2006) – 80% (Distinction)

Transferable Skills

Languages : VHDL, Verilog HDL, Embedded C

Simulation Tools : Modelsim (10.2), Cadence Virtuoso, Cadence Nclauncher Synthesis Tools : Xilinx ISE 14.2, Quartus II, Cadence Encounter Operating Systems : Windows XP, Vista, Windows 7.

Chip Development Tools : Altera DE1&DE2, XILINX Spartan and vertex series Engineering Tools : MATLAB, ORCAD capture CIS, KIEL-C Projects Undertaken

Project 1:“DESIGN AND ANALYSIS OF HIGH SPEED ADDERS FOR FFT PROCESSOR”

Objective: Digital designs are developed based on different design constraints such as speed, power, and area. Among these area is not major criteria in DSP applications. Fast Fourier transform (FFT) is one of the key components for various signal processing and communications applications. A typical FFT processor is composed of butterfly units, an address generator and memory units. This work is primarily concerned with improving the performance of butterfly unit of the FFT processor by replacing the adder structure found in butterfly unit. There are number of adder structures found in digital domain. Different parallel prefix adders are taken into consideration and analyses for power and speed.

Outcome: In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Modern design environments comprises of the design of many high speed ICs which in turn requires being more fast. This project introduces a new approach to redesign the basic operators used in parallel prefix architectures. Designed all the parallel prefix and partial parallel adders and analyse the timing constraints. Then drawn the layout and created the GDS file for fabrication.

Simulation Tool : Cadence Encounter, Cadence Nclauncher

Synthesis Tools : Xilinx ISE 14.2

Chip Development Tool : Spartan 6

Language : Verilog HDL

Project 2:“DESIGN AND CHARACTERIZATION OF KOGGE STONE ADDER IP CORE”

Objective: the kogge stone adder is a parallel prefix adder. The algorithm which uses recurrence doubling technique to design the kogge stone adder. This is based on kogge stone algorithm.it is a type of carry look ahead adder, since the generated and propagated signals are precomputed. In kogge stone adder carries are propagated in tree and fast computation is obtained at the expense of increased area and power.

Outcome: kogge stone adder which generates carry in log n time and the carry tree reduces the logic depth of the adder by essentially generating carry in parallel. It reduces the fan out and critical path of the design. Kogge stone adder is favourable in high performance circuits.

Simulation Tool : ModelSim (10.2)

Synthesis Tool :Quartus II

Chip Development Tool : Altera DE2

Language : Verilog HDL,VHDL

Project 3:“COLOR IMAGE SEGMENTATION USING SEED PIXEL APPROACH”

Objective: Seeded image segmentation is done according to the result of heat diffusion process in which the seeded pixels are considered to be the heat source and the heat diffuses on the image starting from the sources. After diffusion reaches a stable state the image is segmented based on the pixel temperatures.

Outcome: segmenting images using heat diffusion process with an extended anisotropic diffusion method. The development of code using matlab. Semantically meaningful edges with colourful segmentation.

Tool : matlab

Achievements

Have successfully completed mini-projects in RISC processor and Access control system in VLSI design group National Institute of Electronics and Information Technology.

Won third prize in paper presentation on the topic “color image segmentation using seed pixel approach” conducted by national level colloquium on

“trends in electronics and communication.

Attended implant training from All India Radio, Thirunelveli.

Participated in cultural events in school and college level.

Participated in elocution competition at State level. Languages known

Malayalam (Read, Write, Speak)

English (Read, Write, Speak)

Tamil (Speak)

Hindi (Read, Write, Speak)

Personal Details

Father’s Name : Lalichan Thomas

Date of Birth : 16-09-1990

Sex : Female

Nationality : Indian

Permanent address : Thevalacherry House,

Perunna West P.O,

Changanacherry, kottayam

Kerala, Pin: 686 102

Landline No. : 0481- 2423414

Hobbies : stitching, Painting

Declaration

I hereby declare that the above information furnished is true to the best of my knowledge. I assure you I will be loyal to firm I belong and do my duties sincerely. Place: Changanacherry Yours Faithfully,

Date: 16-08-2015 (Lincy L. Thomas)

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