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State University Design

San Jose, CA
April 22, 2016

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OBJECTIVE Seeking an opportunity to work in Digital Systems and VLSI that can strengthen my technical skills ensuring company’s growth ACADEMIC CREDENTIALS

Master of Science, Electrical Engineering January 2014 – December 2015 San Jose State University, CA, USA GPA: 3.41/4

Bachelor of Engineering, Instrumentation and Control Engineering July 2009 – May 2013 Sarvajanik College of Engineering and Technology, Gujarat, India GPA: 8.17/10 GRADUATE COURSEWORK

SoC design and Verification, Advance Digital Design in DSP with FPGA, Advance Computer Architecture, ASIC CMOS design, Digital System Design & Synthesis, Advance Digital Logic, Linear Systems Theory, Probability and Random Stochastic Processes, Semiconductor Devices TECHNICAL SKILLS

• Tools: Synopsys VCS, Design Compiler, Cadence Encounter, NC-Verilog, Xilinx ISE Design Suite, Xilinx Vivado, Altera Quartus 2, ModelSim, MATLAB, Keil 3.0, Visio, PSPICE, Express PCB

• Languages: System Verilog, Verilog, VHDL, UVM, OVM, Perl, C, C++, Assembly, Embedded C, Visual Basic

• Communication Protocols: PCIe, AXI, AMBA(AHB,APB,ASB), SPI, I2C, UART, Altera Avalon, RS 232, PC/AT

• Lab Skills: Oscilloscopes, Power Analyzers, DMM, Signal Generators, Multimeter, Sensors, Probes, Soldering, Instrumentation Devices WORK EXPERIENCE

Design Engineer, Scalable Systems Research Labs December 2015 – Present

• Working with Floating Point Unit Team for a processor and building the complex floating point multiplier in Xilinx Vivado Design Suite

• Designed Wallace Multiplier for reduced the delay on carry propagation by Vertical Slice Compression Technique hence fastening the overall speed of processor

Instructional Student Assistant, Advance Digital Logic Course, San Jose State University August 2014 – December 2014

• Taught Xilinx ISE Design Suite & ModelSim for digital designs to junior students in Advance Digital and Embedded laboratory

• Assist them to resolve queries regarding Analysis and Synthesis of both Synchronous and Asynchronous sequential circuits as well as simplification techniques for Boolean Circuits

• Created assignments, quizzes and their solutions for the course and better understanding of Advanced Digital Logic concepts ACADEMIC PROJECTS

Implementation of Neutron Transport Equations on Altera FPGA, San Jose State University January 2015 – December 2015

• Designed numerical model in Verilog for the equations using IEEE 754 single precision floating point numbers as inputs

• Developed embedded system on Qsys (Quartus 2) to connect NIOS 2 processor with hardware accelerator and SDRAM controller

• Compared the time taken by the host computer and FPGA using Eclipse IDE and GCC compiler on Ubuntu environment MIPS Processor, San Jose State University January 2015 – May 2015

• Implemented five stage pipelined Instruction Set Architecture of MIPS Processor in Synopsys VCS and verified its working with all data hazards and timing analysis in consideration

• Simulated the design for a benchmark program summing the values stored in a memory location and store the answer back in memory Arbitrator for Bus on a SoC, San Jose State University January 2015 – May 2015

• Designed a System Verilog code for arbitrator which permits grant signal for every request signal from master to acquire bus using the arbitration method of Rotating Priority to meet the desired percentage of bus occupancy for each of the nine masters

• Synthesized and simulated the code in Synopsys VCS, Design Vision using UNIX environment Spread Spectrum Correlator Engine, San Jose State University August 2014 – December 2014

• Prepared ASIC design to find frequency and phase of the input spread spectrum signal mixed with other signals below noise floor

• Used 32 correlators that output correlation peaks by comparing input samples with sine wave from PRN generators

• Simulated and synthesized gate-level design in Synopsys VCS, NC-Verilog using UNIX environment and Python 8-bit Scalar Processor, San Jose State University August 2014 – December 2014

• Designed a synchronous digital circuit to implement functions of processor which include read/write, add/subtract, and load/store

• Simulated and synthesized Verilog code, with generating RTL level design, in Synopsys VCS using UNIX environment and Perl script 16-bit Multiplier using only one 4-bit adder, San Jose State University January 2014 – May 2014

• Created a 16-bit add-shift multiplier in ModelSim and synthesized it in Xilinx to maximize the throughput, minimize the area require by FPGA and reduce latency

X-Y Plotter, Sarvajanik College of Engineering and Technology January 2015 – May 2015

• Prepared a controlled pen mechanism using Philips 8051 microcontroller, which was govern by HMI (MS Paint) and analyzes the figure with the help of Image Processing Tool in MATLAB

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