KARMAPANCHAL

Email: acueq1@r.postjobfree.com Contact: 562-***-****

SUMMARY

Experience in writing and updating verification Test plans, Test benches and Test cases to verify the digital designs

Strong knowledge of OOPs concepts, Verilog, System Verilog and UVM based constrained random test bench development

Experience with functional verification closure including functional coverage and code coverage metrics

Experience in writing sequences and tests for internal transactor based bus protocol

Experience in processor based SoC verification and also Sub-system/Block level verification for the respective design

Fixing the bugs related to coverage in internal bus transactor environment

Comfortable working with various simulation/debug EDA tools from Cadence/Synopsys/Mentor, Different version control repository, regression management

Good at debugging test failures and running regressions on various simulator like VCS

Hands on experience in RTL coding, Gate level simulation, Synthesis and Verification

Implemented RTL designs on Xilinx Spartan 3E and Altera DE2 FPGA boards

Strong problem solving skills and debugging experience on digital designs

Excellent interpersonal and leadership skills

SKILLS

Design VLSI/CMOS Design, RTL/ASIC, Logic Synthesis, FSM Model, Standard Cell Characterization, Computer Architecture Verification UVM/OVM, Test Bench Development, System Verilog Assertion (SVA), Coverage, Constrained Random Verification, Functional/Formal Verification, Object Oriented Programming, Static Timing Analysis Programming C, C++, Verilog, System Verilog, Perl/Python scripting, UNIX shell, Assembly (ARM, ISA, x86) EDA Tools Mentor Graphics-ModelSim/QuestaSim, Synopsys-VCS, Xilinx-ISE/Vivado, Cadence-Virtuoso/L-edit, Spice, Microwind, Matlab, LabView, Multisim, Code Composer Studio, Verilog AMS Protocols I2C, SPI, AMBA, APB, Ethernet, PCIe

EXPERIENCE

ASIC Engineer, Scalable Systems Research Labs Inc, USA - San Jose, CA March 2016 – Present

Currently working on developing verification environment using system Verilog and UVM

Acheived coverage models for internal bus protocol as per the verification test plan

Contributed to a team of 4 and coordinated with other teams to design the system

Developed test plan and test benches for different component of FPU

Generated and simulated test cases for the Verilog module

Developed UVM register models to block and system level test benches

Integrated memory models using UVM memory to the test bench

Updated collector, monitor and sequencer as per the verification test plan for the protocol and fix bugs related to coverage in internal transaction based environment

Design Engineer, Sitaram Enterprise, India May 2012 - Mar 2013

Worked with two divisions, and contributed to the verification of high speed serial buses, and CMOS analog/digital design

Achieved functional verification by applying techniques like Assertions (SVA), and Coverage

Developed test bench components like agent, monitor, sequencer, scoreboard, driver in the UVM class library using System Verilog

Transformed CMOS standard cell library from symbol to transistor-level schematic using Cadence Virtuoso tool

Analyzed all the node voltages of the circuit by doing simulation in Spice PROJECTS

Verification of APB (Advanced Peripheral Bus) in UVM using System Verilog, Individual Project Verification of 1x4 Switch RTL (packet based protocol) in UVM using System Verilog, Individual Project

Created the hierarchy of all the test-bench components in UVM using SV-OOP (Synopsys-VCS, UVM 1.2)

Developed test bench components from scratch, which include agent, sequencer, driver, monitor, and a scoreboard

Connected all the test bench components using Transaction Level Modeling (TLM)-ports/exports/analysis-ports

Achieved functional coverage and reduction in simulation time by coverage and assertion techniques Design and Verification of 16-bits Modified MIPS-Lite RISC processor using Verilog, Team Size: 2

Designed and verified single-cycle 5 stages (IF, ID, EXE, MEM, WB) modified MIPS processor

Designed multi-cycle data-path for the processor, and FSM model of the controller

Programmed all the modules (Multiplexers, RAM memory, Register file, ALU, FSM-controller), and their stimulus in Verilog ASIC Boundary Scan Test using Verilog, Team Size: 3

Boundary Scan Test is used for chip-level verification to check open or short circuit connections in an IC

Designed TAP controller-FSM, Instruction Register, and Boundary Scan Register using Verilog in Xilinx ISE

Prototyped the design on Xilinx Artix 7 FPGA

Physical Design, 4X1 6-T SRAM Cell Design in 0.25um CMOS technology, Individual Project

Designed schematic and full custom layout of 6T SRAM memory cell with the sense amplifier in Cadence Virtuoso tool

Analyzed parameters like read/write hold time, power of the memory cell by doing the simulation

Optimized the layout with techniques like sharing diffusion and multiple metal layers which reduced the cell area CMOS Cascade and Differential Amplifier, Team Size: 3

Designed CMOS cascade and differential amplifier (n-and p-channel with current mirror load) in National Instrument-Multisim

Designed considering all the design parameters (power dissipation, slew rate, ICMR, voltage swing limits, small-signal gain)

Studied large-signal and small-signal model parameters in detail for linear analysis Physical Design, Synchronous Counter using 45nm CMOS Technology, Team Size: 2

Implemented gate-level and transistor-level (CMOS) schematics of the 4-bit counter in DSCH tool

Designed full custom layout of the counter using back end software - Microwind

Performed LVS/DRC/QRC checks on the layout using Calibre tool CERTIFICATIONS

SoC Verification using System Verilog, Udemy, USA (License Number: UC-HX5X28YE) OVM and UVM Test Benches, Udemy, USA (License Number: UC-FBVJP3QJ) Python Programming, Udemy, USA (License Number: UC-NAN94C8Z) System Verilog Assertions and Coverage coding in-depth, Udemy, USA (License Number: UC-YFDZMWHQ) EDUCATION

Master of Science, Electrical Engineering Dec 2015 California State University, Long Beach, California, USA GPA: 3.4/4 Bachelor of Engineering, Electronics and Communication Engineering May 2012 Gujarat Technological University, Gujarat, India GPA: 7.16/10

Contact this candidate