Design Engineer

Douglas G. Ndeithi

**** ******* **** ***.,

Tracy, CA 95377

Home: 209-***-****

Cell: 408-***-****

E-mail: acudyx@r.postjobfree.com

OBJECTIVE

Obtain a challenging backend physical design engineering position utilizing my education, ASIC and SOC physical design implementation and verification experience, research and development of ASIC and SOC design flows and methodologies skills, ASIC and SOC physical design troubleshooting and debugging skills, EDA tools experience, script writing skills, methodology and flow documentation skills, writing application notes skills, technical presentations skills, writing training materials and providing training skills. I am eager to learn and quick to adapt to new responsibilities and new technologies, a team player, attention to details, and have leadership skills

EDUCATION

BS in Electrical and Electronic Engineering, California State University Sacramento

AA in Business Administration, Laney College

SUMMARY OF QUALIFICATIONS

EDA Tools Experience

Magma: Blast Fusion

Synopsys : IC Compiler, PrimeTime, PrimeRail, AstroRail, Astro/Apollo, Star-RCXT, Hercules, Formality

Cadence:First Encounter, VoltageStorm, Dracula, Gate Ensemble, Silicon Ensemble, CDC

Mentor Graphics: Calibre, xCalibre

Design Experience

15+ years’ experience in Physical Design implementation and Physical Verification

ASIC and SOC physical design implementation methodology, flow and scripts

Physical verification methodology, flow, and scripts

Proficient in PC hardware and software applications

Programming Languages skills: Perl, Unix, Csh, Awk, Tcl

PROFESSIONAL EXPERIENCE

Exar Corporation, Fremont, California Staff Physical Design Engineer 10/05 – Present

P&R Physical design implementation and physical verification from gate level netlist to tape-out

Writing application notes and providing training

Methodology and flow development, and scripts

FIB preparations and providing instructions

Library preparation and IP evaluation

Tools qualification and evaluation

Developed Big D Small A & Big A Small D (mixed signal) methodology, flow, scripts, and documentation

Analog custom P&R, and layout editing

Backend design lead for the past 2+ years

Timing Closure

Chips: Wireless UART, T1/E1/E3 Framer + LIU telecom combo, PCI UART, PCI Express

Telecom T1/T3/E1/E3 aggregation, Telecom T1/T3/E1/E aggregation and Framer

PMIC(power management IC), HPA touch sensor, SATA, PDH, Hardware security & encryption

P-GAMA display, video surveillance

Independent Contractor, San Jose, California, Design Engineering Contractor 8/05 - 10/05

Independent contractor for Time To Market Inc(TTM) and Synapse Design Automation Inc

Physical design implementation from gate level netlist to gds, and physical verification

QThink, San Jose, California Senior Design Engineer 6/04 – 8/05

Development of Calibre physical design verification flow and automation (perl & csh)

P&R physical design implementation from gate level Netlist to GDSII

Parasitic extraction, physical design verification, and layout editing

Interacting with external customers regarding the designs

Independent Contractor, San Jose, California, Design Engineering Contractor 10/02 - 6/04

Independent contractor for Time To Market Inc(TTM) and Synapse Design Automation Inc

Physical design implementation from gate level netlist to gds, and physical verification

Philips Semiconductors Inc., San Jose, California Senior Design Engineer 6/98 - 10/02

Group lead in research and development of ASIC Calibre physical design verification methodology, flow, and scripting within Philips.

Team player in the research and development of design for Core Re-Use methodology

Team player in the research, development, automation, and documentation of design flow and methodology for parasitic extraction, IR drop analysis, place and route and route, functional equivalency checking, and physical verification

Co-authored scripts to automate the DRC, ERC, Antenna Check, and LVS Calibre physical design verification flow

Team player in providing the first level of support for the San Jose Technology Center on ASIC design issues, parasitic extraction, IR drop analysis, place and route, functional equivalency checking, and physical verification

Debugging and resolving design issues. Liaison between EDA software vendors, intellectual property providers, library providers, and the technology centers

Wrote training materials, application notes, and provided training classes on the operation and interpretation of physical design verification methodology and flow

Intel Corporation, Folsom, California CAD Design Engineer 6/96 – 6/98

P&R Physical design implementation and physical verification from gate level netlist to tape-out

Researching and making technical presentation, and mentoring junior physical designers

Training junior physical designers

Assisted my boss in teaching a layout class at a junior college

Layout editing

Working with CAD and library groups in the implementation of physical design methodology and flow

Chips: Graphic accelerator, chipsets

Packard Bell NEC, Sacramento, California System Engineer 1/96 – 5/96

Test components for computer products prior to production including power supplies, memories,

CDs, hard drives, motherboards, video cards, and fully loaded systems in different configurations and conditions for performance and integrity

City of Roseville, Roseville, California Engineering Student Intern 6/94 – 12/95

Assisted in substation design, load flow analysis using DPAG (Distributed Power Analysis and Grading) software, 60Kv lines design and specifications, material acquisition, and construction details

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