NANDRU PRADEEP email:acudvo@r.postjobfree.com

mobile: 973-***-****

Professional Summary:

Around 6 months of internship experience in VLSI Design and Verification which includes the using of tools Xilinx ISE, Mentor Graphics, Questa simulators by using verilog and introduction about System verilog methodology.

Work Profile:

Working as lab coordinator from October 21, 2014 to till in VERIFxN SOFTWARES Pvt. LTD, Bengaluru.

Technical Skills:

Tools used : Xilinx ISE, ModelSim, Questa Sim.

Programming Languages : VHDL, Verilog

Microcontrollers / FPGA : XILINX Spartan3e, Vertex 4/6

Familiar Protocols : I2C, SPI, UART

OS : Windows, Linux

Educational Qualifications:

M.Tech from JNTUK University, specialization VLSI and Embedded Systems Design.

B.Tech from JNTUK University, specialization Electronics and Communications Engineering.

Academic Project Works:

PROJECT # 1

Title : DESIGN OF DDR3 CONTROLLER

Environment : VLSI DESIGN

Tools : Questa Sim 10.0b

Team size : 4

Role : Team Lead

Project Description :

In computing, DDR3 SDRAM or double-data-rate three synchronous dynamic random access memories is a random access memory interface technology used for high bandwidth storage of the working data of a computer or other digital electronic devices. DDR3 is part of the SDRAM family of technologies and is one of the many DRAM (dynamic random access memory) implementations. DDR3 SDRAM is the 3rd generation of DDR memories, featuring higher performance and lower power consumption. In comparison with earlier generations, DDR1/2 SDRAM, DDR3 SDRAM is a higher density device and achieves higher bandwidth due to the further increase of the clock rate and reduction in power consumption.

PROJECT # 2

Title : An enhanced DMC algorithm

Environment : VLSI

Tools : Xilinx ISE Design Suite 14.7

Team : Single

Project Description :

The main purpose of this project is to develop a enhanced version of DMC algorithm by using ripple carry adder in the section of encoder by replacing adder with ripple carry adder. In this project a given data code word is divided into rows and columns as matrix into ‘m’ rows and ‘n’ columns. By using DMC algorithm, error(s) in the given code word can be detected and corresponding error can be corrected by using binary decimal addition and subtractions.

PROJECT # 3

Title : An enhanced DMC algorithm

Environment : VLSI

Tools : Xilinx ISE Design Suite 14.7

Team : Single

Project Description :

The main purpose of this project is to develop a enhanced version of DMC algorithm by using ripple carry adder in the section of encoder by replacing adder with ripple carry adder. In this project a given data code word is divided into rows and columns as matrix into ‘m’ rows and ‘n’ columns. By using DMC algorithm, error(s) in the given code word can be detected and corresponding error can be corrected by using binary decimal addition and subtractions.

PERSONAL DETAILS:

Father’s Name : N.CHINNA PAPA RAO

D.O.B : 08-11-1991

Passport : L8760833

Marital Status : Single

Current Address : Arekere gate,Bannerghatta road, Bangalore.

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