RESUME

BASIC INFORMATION

Name : Dhivakar B

Phone no :+917*********

Email Id : acud8p@r.postjobfree.com

OBJECTIVE

Intend to build a career in a high tech environment where I can apply my skills and fly high. ACADEMIC DETAILS

Level Stream Institute Board/University

Passing

Year

Degree

% Division

ME VLSI

Pandian Saraswathi

Yadav

Anna University, Chennai, 2014 74.7 % I

Engineering College Tamil Nadu

BE

Electronics &

Communication

PSN College Of

Engineering

Anna University, Chennai, 2011 68.00 % I

and Technology Tamil Nadu

XII Science Stream

Don Bosco Higher

Secondary State Board 2007 73.08 % I

School

X General YWCA Matriculation and Matriculation 2005 72.00 % I Higher Secondary School

TECHNICAL SKILLS

Languages : HDL -- Verilog, VHDL

Scripting – Shell Scripting, TCL.

Backend Proficiency : Physical Design, CTS, STA, DRC,LVS,ERC Operating Systems : Windows,Linux.

Tools Used : Simulation & Synthesis Tools – PSPICE,orcad,Xilinx ISE 8.2i, Model Sim 10.1b, Precision Synthesis RTL 2012b.10.

: Backend Tools -- Mentor Graphics Pyxis Schematic, Cadence Encounter,Tanner FPGA : Spartan 3E.

AREA OF INTEREST

Physical Design

Digital Electronics

ACADEMIC PROJECTS

Title : Design of Efficient FIR Filter using MCM

Platform : VLSI Design During : PG Diploma

Description : Multiple Constant Multiplication (MCM) is an hardware efficient technique which is used to reduce the number of shifts and additions .the objective is that to reduce the area and increase the speed by introducing efficient MCM.

Title : Improved Fault Diagnosis of Interconnects of SRAM Based FPGA Platform : VLSI Design During : M.E

Description : Diagnosing the fault in a application dependent interconnect of SRAM based FPGA. For fault detection a new method called 1 BSF was used and for fault location Mid and search approach was used .By using this method we can achive 98% accuracy.

Title : Design and Synthesis of 32 bit Universal shift register using Verilog HDL Platform : VLSI Design During : B.E

Description : This project presents the design and synthesis report of Universal shift register which integrates SISO,SIPO,PISO and PIPO, using verilog coding with the help of model sim for simulation and Precision synthesis tool for RTL synthesis.

SHORT TERM COURSE

PG Diploma in VLSI Design from Centre for Development of Advance Computing (CDAC),Noida. (2015). Diploma in Hardware and Network Engineering from Accel IT Academy ( 2012). OTHER INFORMATION

Worked as a System Engineer at TVS Infotech Madurai. Participated in an International conference on emerging trends in Electronics at PSYEC. Hockey and Cricket player during my College days.

PERSONAL INFORMATION

Address : S/o Balakrishnan A,1/76,Arumbanur po, Nationality :Indian Agricultural college via, Madurai, Sex :Male

Tamil Nadu – 625104 . Marital Status :Single

Languages Known : English, Tamil(Native), Malayalam,Hindi, Spanish(Beginner level). DECLARATION

I here by confirm and declare that the details furnished above are true and correct to the best of my knowledge and I assure to work actively towards the development of the concern. Signature

Dhivakar B

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