Design Engineer

Bharath. D. V

#*, ******** *********,

Central Exercise Layout, Off Doddakammanahalli

Main road, opposite to kidzee

Bangalore - 560076

Phone: +918********* Email: ***********@*****.***

Objective

To achieve a position which gives me an opportunity to gain experience and expand my knowledge while creative solutions to the advancement of organization to pursue a challenging career in ASIC Verification.

Skill Sets:

Languages

Verilog, System Verilog

Protocols

AMBA AHB, UART

Tools

Questasim, Xilinx

Education

§Bachelor of Engineering (B.E.) in Electronics (SDM College of engineering, Ujire) from V.T.U. passed out in July 2015 with 60.11%.

§Diploma in Electronics and communication (DVS polytechnic, Shimoga) from Board of Technical Education passed out in June 2012 with 67.44%

§S.S.L.C. (Class 10th) from Karnataka state board from Lions High School, Ranebennur passed out in March 2008 with 72.86%.

Core Competency

§Knowledge of digital logic design

§Good Knowledge in Verilog and system Verilog.

§Hands on Experience in creating verification environment using system Verilog.

§Keen in learning new technologies and adapt to same as soon as possible.

§Good Knowledge to review and use tools for the given design process.

§Strong knowledge of CMOS circuit designing.

Work Experience

§Worked as an Junior Design Engineer(Intern) in Nano Scientific research centre from June 2015 to December 2015

Projects worked in Nano Scientific Research Centre

1.AMBA AHB Design and Verification

Tools Used: QuestaSim

HDL: system Verilog

Role and Responsibilities:

§Understand the requirement and come up with the verification plan.

§Create a testbench and verify the given DUT using a system Verilog test environment.

§Adding test to check the functionality of the IP.

2.DESIGN OF UNIVERSAL ASYNCHRONOUS TRANSMITTER AND RECEIVER (UART )

Tools Used: Xilinx

HDL: Verilog

Role and Responsibilities:

Understand the specification of UART

Design the UART code using Verilog.

BE project

Title: ADVANCE ATM MACHINE

Team Size: 4 members Role: Lead Developer

Objective:

Code the Advance ATM Machine using Ladder program to give security alert for the users.

Description:

RF Transmission and receiving is done with ATM’s which will help us in having alerts. With those alerts a message is sent to the protection force.

Strengths

I have the ability to cope with failures and try to learn from my mistakes;

To lead from the front and always open to new ideas;

Eager to learn and improve constantly;

Adaptable to any environment and location; and

Self-disciplined Sincere, Punctual, Honest and Friendly.

Achievements

Presented a paper entitled “sunami warning system ” at Intercollege compitation on Electronics and Communications

Attended Workshop on VLSI design.

Personal Information

Date of Birth : 05-09-1992

Gender : Male

Father name : Vijayakumar

Mother name : Vijayavani

Mother tongue : Kannada

Nationality : Indian

Languages known : English, Kannada, Hindi.

Permanent address : S/o Vijayakumar D

Near Gupta PetolBunk

UmashankarNagar

Ranebennur-581115

Karnataka.

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

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