Engineer Quality

KANAK SARMA

*** ****** ****** ***** 508-***-****

Northboro, MA 01532 **********@*****.***

I’m a strategic thinking professional with 20+ years of experience in quality, manufacturing, and R&D in semiconductor and diverse technologies. Recent focus is on product quality management, supplier quality, QC/QA, customer relations, corrective action implementation, and problem resolution. Demonstrated successes are in product development, reliability, and Yield Enhancement. Extensive travel experience to cover Japan, Taiwan, Europe & US customers.

SPECIALTIES

New product introduction, System and product quality, operation

Supplier Quality, Quality Audit, High Risk Supplier Problem Resolution, MSA, APQP/PPAP

8D, 5 Why, 5S, FMEA, SPC, Process Capability, Oracle, Agile, ISO/TS, CMM

Statistical Analysis (Minitab, SAS, RS1), Lean Six Sigma (ASQ certified)

Ceramics, Li-ion Batteries, Semiconductor device and processes

Technical Marketing and Applications, Project Management, Customer Relations

Process Integration, Yield Enhancement, Technology Transfer, Reliability

Foundry Services and Supplier Management, Program Management

2 US Patents and Awards.

EXPERIENCE

CoorsTek, Worcester, MA 2014 – Present

Quality Assurance Engineer

CoorsTek develops and manufactures advanced Ceramics and Anodized Metals for Semiconductor equipment markets.

Managed Quality Assurance by providing leadership, management, and expertise in all quality aspects in the manufacture of products per customer requirements.

Reduced scrap reduction effort to down to 1% of sales from more than 7% year ago. Saved the company over half million dollars over a six month period as direct revenue.

Improved New Product Introduction (NPI) procedures in all aspects from quotation order, design through production planning, packaging, and quality control for on time delivery.

Managed day-to-day quality operation control and assurance by closely collaborating with engineering, manufacturing, planning, and sales organization.

Implemented product and system level quality improvement by poke-yoke, FMEA, problem resolution, and control plan.

Managed testing correlations among instruments, GR&R, and CMM analyses. Solved design level faults per specification control, process effect, and measurement.

Employed SPC, implemented SOPs based on audits, NPI, and problem solving.

Managed one technician.

A123 Systems, Westborough, MA 2009 – 2013

Sr. Supplier Quality Engineer

A123 Systems develops and manufactures advanced Nanophosphate lithium ion batteries and battery systems for the transportation, electric grid services, and consumer markets.

Managed supplier quality audit as supplier selection process for domestic and overseas suppliers per automotive industry oriented Advanced Product Quality Planning (APQP) and control plan. Implemented internal audit for ISO 9000 qualification.

Managed approved Vendor List (AVL) by supplier audit, ISO qualification, and in collaboration with supply chain and engineering.

Successfully used Oracle/Agile system for coordinating and controlling quality issues (in-line and field- all sites) of the ESG Grid inverter (2MW and 4MW) for problem resolution (8D) and process changes. Investigated components on the printed circuit boards for failure analysis, corrective action and presented to customers.

Worked with the environmental group for ROHS, REACH, and China REACH document control.

Controlled non-conformances of high risk suppliers in US and China including proactive audits. Problem solving used are printed circuit boards (PCB) and at the PCB supplier houses.

Successfully completed PPAPs as well as covered IMDS and CoC (compliance) with the compliance group and document control (ECN).

Performed module and pack MSA analyses of critical tools as well as advised on MSA (GR&R) and process capability studies.

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ALLEGRO MICROSYSTEMS, Inc., Worcester, MA 2003 – 2009

Principal Quality Engineer

Responsible for decision making for QC/QA of wafers manufactured/shipped to customers by all internal/ external fabrication plants and assembly houses worldwide. Market segment contains automotive sensors needing quality guarantee to zero ppm.

Material Review Board: Led MRB actions on inline fab (manufacturing fabrication) and external assembly related issues for problem resolution including maverick (deviation) materials.

Quality Control: Dispositioned materials per quality control specifications and guidelines, electrical tests and sorts. Implemented accept/reject criteria of outgoing/returned materials. Reviewed, advised, and played consulting role in wide variety of data, material, and failure analyses.

Quality Defect Reduction: Drove through and implemented defect reduction such as scratch defects used for customer’s notification on continuous improvements and benefits.

Foundry Evaluation: Rated external foundry performance based on problem resolution and corrective action implementation.

INSPEX, INC., Billerica, MA 2000 – 2002

Product and Applications Manager

Responsible for product and applications for Defect/Yield Management software used in semiconductor manufacturing and R&D fabs worldwide. Developed a parametrics software package for in-line fab process measurement comprising photo, interface, films, e-test, sort, and final tests by using in-fab experiences.

Product Development: Managed evolution of new product specifications for customer needs, requirements, and product benefit to customer. Directed products for statistical yield analysis, bit map, spatial pattern recognition, SPC, and data mining to processes 0.13 m.

Applications: Prioritized demo, development, and product improvement activities, technical and application notes.

Engineering Interface: Taught/ developed awareness of customer use, market forces, and needs. Managed customer inputs and prioritized product improvements. Directed and kept abreast of various engineering projects.

Patent: Successfully helped company obtain patent on a product (unresolved for >1 year).

CHARTERED SEMICONDUCTOR MANUFACTURING, INC., Waltham, MA 1999 – 2000

Engineering Account Manager

Responsible for technical interface and focal point of communication between customer/factory to ensure product performance, yield, quality, and reliability during prototype/production. Delivered technical presentations to potential and existing customers.

Directed resolution of gate oxide integrity and silicon interface issues by process modification, charge to breakdown, and surface analyses of SEM, TEM, and photon emission microscopy for an automotive sensor product.

Performed extensive design tape-out from customer to manufacturing using GDSII files across various technologies including BiCMOS and CMOS to 0.18 m.

Evaluated design rules, electrical parameters, models, processes, and qualifications to determine fit to factory capacity.

INTEL CORPORATION, Hudson, MA (Formerly Digital Equipment Corporation) 1987 – 1999

Senior/Principal Engineer

Led process integration, device, yield enhancement, and process reliability from start-up projects to full implementation. Significant experience in e-test characterization of transistor, isolation, interface, surface and in-depth failure analyses. Responsible for excursion management of CMOS products – SRAM, cache, and microprocessors.

Led implementation of Wafer Level Reliability (WLR) including test structure design, development, and reliability for time zero dielectric breakdown, oxide integrity, electromigration, and mobile ion at the device level to optimize and qualify processes. (published work)

Analyzed statistical process experiments using SAS and RS1. Provided manufacturing with technical direction, design of experiments (DOE), and problem solving methods on root cause identification and corrective action.

Led defect-density (D0) based SRAM yield model project for periodic reports on product yield impact pareto for project prioritization. Helped streamline WORKSTREAM.

SOLID STATE SCIENTIFIC, INC., Willow Grove, PA 1983 – 1987

Senior Development Engineer

Advanced Process Development

Developed dual-poly CMOS EEPROM process, designed EEPROM cells, P-well 4-T SRAM process, and 256K ROM process (product of the year award from the Electronic Products magazine, 1984). Won patents on EEPROM cell design and process development.

Developed tungsten-silicided gate, multilayer metal, and thin gate dielectric processes.

EDUCATION

M.S. Electrical Engineering (EE), RPI (Rensselaer Polytechnic Institute)

M.S. Physics, RPI (Rensselaer Polytechnic Institute)

AWARDS

Digital’s distinguished award for process simplification

Product of the year award from Electronic Products magazine for SCM23C256

PATENTS

EEPROM Cell design and Process Development

U.S. Citizen

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