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Engineer Software

Location:
San Jose, CA
Posted:
April 11, 2016

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Resume:

Leonard Bong

***** *** ***** ******* **, Los Gatos, CA 95032

Home: 408-***-**** – Cell: 408-***-**** -- acua0e@r.postjobfree.com

Professional Summary

Senior software engineer

Architected, designed, and implemented physical design verification flow for ASIC design by integrating design tools from Synopsys and Cadence to meet IC design team specific needs.

Architected, designed, and implemented memory compiler software for memory design team as an in house tool

Implemented backend manufacturing flow for scribe-line, reticle, wafer maps, and generation of stepper job to drive the stepper machine for 8" and 10" wafer.

Managed a team of software engineers to design wire bonding and flip chip manufacturing flow.

Side Job

oJoin HNL-Ventures developing software tools for predicting stock market on Windows 7 using C, MySQL, php and python. Responsible for setting up and maintaining Database using MySQL.

Core competency

oC language, Perl, TCL/TK, Python/QT, Csh Scripting, SQL (Sybase, Oracle, MySQL)

oLinux/Unix, Windows

Experience

Software Engineer

HNL Ventures (June 2010 – Now)

Part time (Side work) for HNL Ventures, a startup company in the stock market field.

oEnvironment – Window 7

oLanguage – C, Python

oRDBMS -- MySQL

Principal Software Engineer

Oracle (November 2013 – January 2015 (1 year 3 months) – Santa Clara, CA

Backend verification flow for deep sub-microns processes

oImplemented Re-Tape-out Flow for 20NM process node using Mentor Graphics Calibre verification tool.

Environment – Linux

Language – TCL/TK

RDBMS -- MySQL

o* Implemented Cut OD Flow for 16NM process node in Mentor Graphics Calibre verification tool.

Environment – Linux

Language – TCL/TK

RDBMS -- MySQL

o* Implemented queuing system in "Inter-active" Graphical User Interface tool, where the tool will maintain multiple submitted verification jobs in queue and dispatch them one at a time to avoid using multiple Calibre's licenses, and to avoid overlapping of output.

Environment -- Linux

Language -- TCL/TK

RDBMS -- MySQL

oSupport, Maintain, and Enhancing GDS Application

Environment -- Linux

Language -- C, C++

Sr. Software CAD Engineer

Texas Instruments (July 2011 – July 2013 (2 years 1 months) – Santa Clara, CA

Collaborated with R&D group to design, develop and QA the tool for transformer/inductor optimization and synthesis tool using mathematical equation based to calculate the inductance value given other physical parameters (i.e. metal width trace, metal spacing trace, and number of turns) and vice versa for fast turn-around prototyping, before running actual simulation. The tool was written in Python and Qt4 with graphs comparison for various results.

oEnvironment -- Linux

oLanguage -- Python & PuQT4

Took over existing Memory Compiler software created by TI software team and collaborated with memory designers to enhance the tool to support additional EDA views (Mixed Signal Verilog, Cadence EPS for IR Drop analysis) for IC design digital tools flow.

oEnvironment -- Linux

oLanguage -- C, Perl

oRDBMS -- MySQL

Software CAD Engineering Manager

National Semiconductor (August 1984 – July 2011 (19 years 10 months) – Santa Clara, CA

Collaborated with memory designers to design, architect and develop “Memory Compiler” software which has the capabilities to generate various design views, such as layout in GDS and Cadence CDB and OADB, Schematic, EPS, LEF, CDL Netlist, Datasheet, Liberty, Timing verilog, Milkyway, and interface to Synopsys P&R tool for verification

oEnvironment -- Linux

oLanguage -- C, hiDB scripting (Internal language, similar to TCL)

Project leader to develop “Reticle Generation” system tool by collaborating with multiple fabrication sites and mask making group to define the specification, and worked with remote site software group to design, implement and QA the system which has the following capabilities:

oCreates scribe-line with and without test patterns according to each fab site's spec.

oCreates optimum reticle with maximum number of dies with and without test pattern according to each fab site's spec.

oCreates optimum wafer map with maximum number of dies and less steps to maximize the stepper machine through put.

oCreates stepper job control deck that can be feed directly to the stepper machine.

oCreate Mask Order Form

oUsing Sybase’s RDMBS as the back-bone database to store the data where the fab's operator can down load the information from.

oEnvironment -- Linux

oLanguage -- C, TCL/TK, csh Script

Project leader to develop “TapeOut Cockpit tool“ that run final verification flow (such as DRC, ERC, Soft-Check, LVS for both Cadence Assura and Synopsys Hercules tools) on a design before mask-making process, according to each process technology's verification flow to ensure the design is verified and meet technology design rules. The process design rule is provided by process design engineer and captured/stored in Oracle RDBMS.

Managed a team of CAD engineers to develop standard cell library characterization flow.

Managed a team of CAD engineers to develop front-end IO library cell checker.

oEnvironment -- Linux

oLanguage -- C, TCL/TK, csh script

Proficient

Environment

oLinux/Unix

oMicrosoft Windows 7

Visual Studio

Software programming language

oC

Scripting Language

oTCL/TK, Python, Qt4, Shell script, Java, PHP, Cadence’s skill language(training)

oHTML, JavaScript programming

Database

oRDBMS (Sybase, Oracle, mySQL)

Revision Control

oPerforce

ovcs

Education

BS Computer Science

January 1980 – April 1982

Central Michigan University

MS Computer Science

August 1982 – December 1983

Central Michigan University



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