Engineer Manager

Present Address:

*** ******* **.

Milpitas, Ca **035

Home: 408-***-****

******@*****.***

Education:

University of California, Berkeley B.S. in EECS 1982

San Jose State University M.S. in EE 1987

Objective:

Sr. Program Manager

Work Experience:

1/09 – Current Various companies(Brite Semi, Gerson Lehrman Group, Bain)

Engineering Consultant

Consultant service includes business plan for designing CPU & graphics controller projects, writing SOC project

plan, power & performance tradeoff, reviewing designs, resource planning, project scheduling, and resource allocation, and etc. Other activities include die size and gate count estimation, timing evaluation, technology determination, resource allocation, schedule planning, micro-architecture, coding, synthesis, verification, etc.

Most current activities are drafting technical documents for promoting client's IPs portfolios.

6/06 – 1/09 ARM

Principal Engineer/Consultant

Design and Architect TestChip - IP integration for silicon validation.

Tasks included front-end architecture, logic design, RTL coding, synthesis, verilog simulation, formal verification, test bench development, timing analysis, floorplanning, package development and silicon debug.

Testchips contained standard cell structure, memories, MBIST, and complex digital and analog IP such as PLLs and high speed I/Os. Technology: from 90nm to 45nm with various foundries.

IP's quality has improved significantly through the use of new design methodology.

8/03 – 12/06 Various Companies(ARM, IP-Value, MoSys)

ASIC Consultant

Consultant service for ASIC development including business and engineering issues.

Tasks included budget forecast, product planning, project scheduling, resource allocation, venders interfacing, patents reviews, product definition, micro-architecture, behavior modeling, RTL, verification, synthesis, timing analysis, floor planning, test pattern development, silicon debug, etc.

Designing Test Chips for ARM - integrating standard cells, peripheral pads, analog circuitry, and memories

Reviewing technical patents for IP Value - including circuit design to logic design to subsystem design, and then

summarized the inventions and research companies in violation of patent right.

Modeling memory IPs for MoSys - cycle and timing accurate top level behavior modeling, tasks included test bench setup, verification, and regression testing; also reviewing the design methodology and CAD tools for the company.

3/01 – 7/03 TVIA Inc.

ASIC Development Director

Responsible for CAD/Design Methodology, CPU and 3D groups for MPEG Set-top box & LCD controller products

Management responsibility included product planning, project scheduling & planning, venders interfacing, budget forecasting, resource allocation and planning, hiring, and managing engineering teams.

Provided leadership and innovative ideas on the ASIC design methodology, set-up & implemented ASIC design flow, and saved multi-million dollars on CAD tools through effective price negotiation from purchases, and provided guideline, training & support to the design teams.

Managed CPU and the 3D teams to develop IP cores for integrating with the next generation SOC Set-Top-Box products. Hands on engineering activities included CPUs (SH4 and SPARC) RTL coding, synthesis, timing analysis, functional verification activities included modifying test benches for simulation, acceleration, test & emulation, and assisted other projects in various aspect of engineering issues.

Managed over 20+ engineers, and managers, included engineering contractors, venders, and oversee Engineering teams in China and worked with various foundries like UMC and TSMC.

Worked closely with software engineering on firmware and application development

Worked with marketing on product definition, customer interfaces, and product documentation and worked very closely with application group on board design.

3/00 – 3/01 Philips, Trimedia Technology Inc.

System ASIC Director

Defined high level plans, direction, deliverables, resources, tools and schedules for hardware engineering

Interfaced with various companies for joined system and IP development

Designed and architect a chip with Trimedia 64-bit VLIW processor and MIPS processor and various peripherals

Involved in chip architecture definition, RTL design and verification activities, and provided technical leadership in the area of ASIC implementation, verification and layout.

Worked closely with sales and marketing on product definition and customer support related matters.

Board member of the NAPA project, a next generation advanced prototyping development system for ASIC and NXP development.

2/99 – 3/00 AdvanSys(Advanced System Products) Inc.

ASIC Hardware Director

Managed PCI-SCSI IC products for RAID application system

Defined project architecture, specification, and schedules

Managed resources - included hiring, interfacing various venders and contractors, budgeting, planning, etc.

Projects included a chip-set of XOR-cache controller and PCI-SCSI controller, and a single integrated RAID controller chip with embedded MIPS microprocessor to run RAID application

Filed patent on Caching Techniques for RAID application system

Provided detail engineering specification document and supports for design and verification team, and worked with application and system groups on the system board development.

Worked very closely with software group on firmware and application software development

Managed the ASIC design, verification and backend layout teams

Worked with marketing on product definition and product specification

8/97 – 1/99 Chips & Technologies Inc.(Intel)

Micro-Architecture Manager/Principal Engineer

Chief micro-architect for the desktop Flat Panel Controller

Defined project specification including algorithm, tradeoff, and design specification

Developed functional modeling and interacted very closely with software, marketing and system teams.

A system-on-a-chip project included A/D, embedded microprocessor, sdram controller, and so for.

Developed high quality image scaling algorithm and method of handling Frame Rate Control.

Documented detail engineering specification and provided supports for design and verification.

Managed micro-architecture team and reported to the department Senior Director.

1/94 – 8/97 Integrated Device Technology Inc.

Project Manager/Design Manager

i) In Microprocessor Division

Managed MIPS R4600 chip set – a PCI bridge chip and a memory controller chip

Managed DirecPC project – a set top box embedded micro-controller includes MIPS R3041 core,

transport, peripherals, etc. for satellite receiver board on a PC.

The project tasks included defining spec., customer interface, cost estimation, scheduling,

resource planning, managed a team of engineers, defined design methodology, logic and

circuit design, simulation, etc.

ii) In SRAM Division

Managed and designed a cache controller for Pentium laptop computer

Coordinated several groups to setup ASIC design methodology for this project

Setup verilog simulation environment for chip verification, synthesized logic using Synopsys,

optimized logic by hand for speed, P&R, etc.

Provided ASIC expertise to the department and setup the design libraries for Verilog and Synopsys

2/90 – 1/94 C-Cube Microsystems Inc.

Senior Design Engineer

i) CL9100 MPEG2 decoder – designed DRAM controller

ii) CL4000 MPEG1 encoder – defined and designed host bus interface

- adopted NuBus like protocol and architected for multichip design

iii) CL950 MPEG1 decoder – defined and developed a 32bit risc cpu core

- microarchitected, coded, debugged, synthesized, logic design, p&r, etc.

- designed a fast 32bit ALU datapath and specific instruction set for the MPEG decoder

iv) CL550B JPEG encoder and decoder

- designed the zip-zap module and developed a fast VLC and VLD implementation

6/88 – 1/90 Fujitsu Microelectronics Inc.

Project Leader

i) 40MHz SPARC IU – designed and synthesized instruction unit control and led the backend & timing activities

ii) 33MHz SPARC IU – led the development team on this design effort – involved with all aspect of the design

3/86 – 5/88 Weitek Corp.

Senior Design Engineer

i) Project lead on WTL3167 – 25MHz CMOS floating point coprocessor, up to 8MFLOPS performance

Lead engineer on this project and coordinated all design activities.

ii) Debugged and redesigned WTL1167 chip set – 20MHz NMOS scalar floating point processor (ALU & MUL)

5/84 – 2/86 Modular Semiconductor Inc.

Design Engineer/CAD Manager

Designed circuit and logic for the projects below plus managing CAD tools and layout activities

i) Custom Design – Custom Video Processor

ii) Computer Peripheral Design – VME Bus Interrupter Module

iii) Memory Design – 256K x 1 CMOS DRAM

8/82 – 5/84 Hewlett-Packard

R&D Development Engineer

i) Redesigned an I/O Processor for HP1000 computer – redesign from SOS to bulk CMOS

ii) Designed a processor support chip for HP plotter

iii) Standard Cell Design and Methodology Development

References:

Available upon request

Other Skills:

Computer Languages: BASIC, FORTRAN, Machine & Assembly, Verilog

CAD tools: SPICE, Timemill, Synopsys, Verplex, various P&R tools, signalscan, etc.

Memberships:

Member of IEEE and UCSEE(U.C. Society of EE)

Work Summary:

Over 33 years experience in IC industry, 16 years in management and 17+ years in design engineering and engineering lead. Expert in managing ASIC/IC development and turning projects in successful products. Experience in building and managing design teams, working with partners and foundries, and dealing with oversea companies. Market involvement included CPU/microprocessor, multimedia SoC, LCD display, set-top-box, and memory products. Excellent communication skill, work well with people, and experience in dealing with customers and venders.

Currently serving as a member of the Telecommunication Commission for the City of Milpitas and VP/COO for Milpitas Community TV.

Full of imagination and other special talents that are relevant.

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