Design Engineering

CONTACT B/**, Charkop Vishnu Kutiya,

Charkop

Sector-1, Kandivli (west)

Mumbai-400067

E-mail: *************@*****.***

Phone: 771-***-****

OBJECTIVE Seeking an entry level job position in a reputed engineering firm in order to build a long term career by investing best of my technical knowledge and other qualifications and to serve the organization with an outstanding output. QUALIFICATIONS Completed Post graduate Diploma in VLSI Design (PGD-VLSI) from C-DAC(Center for Advanced Computing and Development) .

B.E(Electronics) (2015)

Pravara Rural Engineering College,Loni, University of Pune. Modules include: Digital Electronics,Solid state devices and circuits, Integrated circuits,Data structures,Power Electronics,Micro

controllers(8051,PIC),Microprocessors,Communication Theory,Data communication,Digital Signal Processing,Electronic Product Design,Embedded systems,

VLSI.

Percentage = 63.46%

Passed Higher secondary examination(HSC) in Science stream under Maharashtra state board with 61.67%.

Passed Secondary examination(SSC) under Maharashtra state board with 70.13%. OTHER

QUALIFICATIONS

Completed Diploma in "Embedded systems" from IDEMI (Institute for Design

& Electrical measuring instruments) with grade B+ ( 75-80 %). ACADEMIC

PROJECTS

1) Immediate Traffic Light Controller using RF modules (3rd year). Controlling the traffic lights with the help of Radio frequency Transmitter and Receiver modules in order to let the Ambulance pass without any delays or obstacles during medical emergency.

2) FPGA based High speed, Low power 32*32 bit multiplier (4th year). A mixed number representation is being used in a High speed and Low power multiplication algorithm.The redundant binary (RB) adder and booth decoder along with sign magnitude notation of the multiplicand,helps in achieving the reduced switching activity and low power dissipation. The high speed operation is achieved by accumulation of partial products (PP) through carry propagation free (CPF) using RB notation. Due to this, the switching activity during the PP generation process can be reduced on an average by 90%.The design proposed in paper dissipates much less power comparatively and is 18% faster on an average.Spartan-3 FPGAs have a Sucheta Sinha

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number of features to fortify the chip’s arithmetic capabilities. Carry logic and dedicated carry routing continues to be provided as in past generations. Dedicated AND gates in the CLBs accelerate array multiplication operations. 3) Line follower Robot using VHDL coding and Virtex-5 board (C-DAC-Minor project).

A simple line follower robot with the help of l293d ic and IR sensors.This was one of the attempts to closely observe the efficiency of an FPGA Board. 4) Building custom FIR filters using System Generator(C-DAC-Major project). System Generator is a high level design tool well suited to creating custom DSP data paths in FPGAs. While providing a high level abstraction of an FPGA circuit, it can be used to build designs comparable to hand crafted implementations in terms of area and performance.We are trying to demonstrate how an algorithm can be efficiently mapped onto FPGA resources and present the hardware results of several System Generator FIR filter implementations.

VLSI FIELD

SKILLS

1. VHDL Coding;

2. Verilog Coding;

3. Perl scripting;

4. Shell scripting;

5. Advanced Digital Design;

6. Static Time Analysis;

7. Basics of System Verilog;

SOFTWARE

PROFICIENCY

Languages known : C programming; C++ programming;

Operating system : Windows 7,XP, Linux;

NON TECHNICAL

SKILLS

Excellent Communication skills;

Analytical skills;

Comprehensive problem solving ability;

TOOLS WORKED

ON

Microwind 3.5

Modelsim Altera 6.3

XILINX 13.2

XILINX 14.7

ACHIEVEMENT Published a paper in International Journal of Multidisciplinary Research and Development on "FPGA based High speed,low power 32*32 bit multiplier". EXTRA

CURRICULAR

ACTIVITIES

Won accolades in Debate competitions.

Quiz Competition.

Actively participated in College Gathering.

Organized and Coordinated technical and cultural events. Paper presentation during during technical events in other colleges. Suche ta Sinha 2

AREAS OF

INTEREST

1. VHDL Coding;

2. Verilog Design;

3. Digital Logic Design;

4. Physical Design;

5. CMOS layout Design;

6. Micro-controllers;

STRENGTH Adaptable to any work environment.

Hard working.

Patient.

Dedicated and focused till my work gets complete.

HOBBIES Writing short stories/screenplays.

Music.

Painting/Sketching.

Photography.

Travelling to new places.

LANGUAGES

KNOWN

1. English;

2. Hindi

3. Marathi;

4. Bengali;

REFERENCES None.

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