Electrical Engineering State University

Jord Fumar

**** ********* ****,

San Jose, California, 95116

925-***-****

****.*****@*****.***

www.linkedin.com/in/jfumar/

Objective Seeking an internship or full time position in Electrical Engineering Education BS in Electrical Engineering, San Jose State University, December 2015 Relevant Coursework : Embedded System Design, Microelectronics, Electronic Control System Theory, 8086 and 8088 Microprocessor Architecture. Electronic Design, Signals and Systems, Linear Systems

Skills Tools : AVR Studio 6.1, LTSpice IV, EAGLE 2.0,Python,Matlab, Xilinx ISE 14.2, Isim, Programming Languages : C++, Verilog

Lab Equipment : Oscilloscope, Function Generator, Digital Multi-meter Operating Systems : Windows XP, Vista, Windows 7

Office Applications : MS-Word, MS-PowerPoint, MS-Excel Work

Experience

Manufacturing Test Intern, Tesla Motors, Palo Alto, CA (05/2015 - 08/2015)

● Designed Software Test Platform for CAN/Firmware ID Test Sequence for Model S/X Serial Mono CAM using an ARM based microprocessor

● Implemented a C++ Filter Algorithm on an MBED microcontroller to effectively receive CAN signals over high traffic in the bus

● Developed a program in C++ for automating ICT-FT test log comparisons.

● Assembled portable flash kit for Door Modules(DDM/PDM) and Seat Modules.

● Troubleshooted test fixtures for Front Door Modules by verifying genealogy block using Tesla Firmware Download Tool.

Relevant

Projects

Embedded System Design and Implementation of a simple Analog to Digital Signal Converter

● Designed circuit interface using four D-type octal latches (74LS373), one 8-bit ADC 0804 chip, a chip select circuit using an inverter (74LS04) and Decoder (74LS139), and four 7 segment display.

● Developed C++ code confirming valid inputs from ADC, tested chip select circuit and memory functions, implemented software via Devasys USB-I2C/IO.

● Successfully performed Analog to Digital signal conversion, displayed converted value to LED display.

Implementation of a Time Multi-plexed 7 Segment Display using Basys 3 FPGA

● Implemented a 8 input 12 output multi-plexed circuit in Verilog using Vivado 2015.2

● Performed Synthesis, incorporated User Constraint File and Testbench XDC file, and generated bit file

● Successfully flashed Basys 3 FPGA with the bit file and confirmed multiplex functionailties of the 7 Segment Display

Contact this candidate