Design Engineering

Suruchi N. Patel

**, ******* ***** ******, ******: +91-966*******

Arekere,Bengaluru, Karnataka- 560076 Email: *******.********@*****.*** Career Objective:

To seek a position as VLSI Engineer in an organization where I can contribute my skills for organizational development as well as my professional career growth. Academic Qualification:

• Master of Technology in VLSI Design 2014

Yeshwantrao Chavan College of Engineering, Nagpur, Maharashtra

--Cumulative Percentage: 7.57(CGPA)

• Bachelors of Engineering in Electronics & Communication 2012 Jhulelal Institute of Technology, Nagpur, Maharashtra

--Cumulative Percentage: 65.60%

• Higher Secondary, Science 2008

Bhide Girls jr. College, Nagpur, Maharashtra

--Cumulative Percentage: 65.67%

• Secondary 2006

Vidya Mandir High School Koradi, Nagpur, Maharashtra

--Cumulative Percentage: 82.66%

Professional Certification:

Maven Silicon Certified Advanced VLSI Design and Verification Course From: Maven Silicon VLSI Design and Training Center, Bangalore Projects Handled:

1] AHB2APB Bridge IP Core Design and Verification

HDL: Verilog.

HVL: System Verilog

TB Methodology: UVM

EDA Tool: Revera-PRO, Questa Sim and Xilin-ISE

Description: The AHB to APB Bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses

Architected the design

Implemented RTL using Verilog HDL

Architected the class based verification environment in UVM

Verified the RTL module with single master and single slave

Generated functional and code coverage for the RTL verification sign-off 2] AXI UVC - AMBA AXI4 Protocol Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tools: Revera-PRO, Questa Sim

Description: The AMBA AXI protocol is targeted at high-performance, high-frequency system and includes a number of features that make it suitable for a high-speed submicron interconnects.

Architected the class based verification environment in UVM

Verified the protocol with single master single slave environment 3] Router 1x3 – RTL design and Verification

HDL: Verilog.

HVL: System Verilog.

TB Methodology: UVM (Universal Verification Methodology). EDA Tools: Revera-PRO, Questa Sim and Xilin-ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Architected the design

Implemented RTL using Verilog HDL and Synthesized the design

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog

Academic Projects:

Design and Analysis of 32-bit Carry look ahead adder using Constant delay logic style M.Tech Thesis under the guidance of Prof. M. S. Pawar EDA Tools: Tanner Tool

Description: The 32-bit CLA adder with Constant delay logic style circuit based on 0.18 µm CMOS process is implementing for low power consumption and high performance over the other logic style.

Design schematic and Simulation of 32-bit CLA adder with CD logic and CMOS logic using Tanner Tool v13.0

Analyzed simulation results of both logic styles in T-spice Density Based Traffic Light Control & Security Protocol Using RFID B.Tech Thesis under the guidance of Prof. M. Parkhi Description: A microcontroller based system is developed to check the density of the traffic and the security system using Rf id is interfaced to the microcontroller. Technical Competency:

HDL : Verilog

HVL : System Verilog

Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA

TB Methodology : UVM

EDA Tool : Xilinx-ISE, Questa Verification Platform, Rivera-PRO, Tanner Tool Domain : ASIC/FPGA front-end and Back-end Design and Verification Knowledge : Static Timing Analysis, RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage and Synthesis Work Experience:

Internship: Maven Silicon VLSI Design and Training Center, Bangalore (Jan 16–To present) Lecturer: G. H. Raisoni Academy of Engg. & Tech., Nagpur (Dec 2014 - June 2015). Publication:

“Design of Constant Delay Logic Style for High Speed Adder”, at IEEE International Conference on Green Computing, Communication And Electrical Engineering

(ICGCCEE’14), Coimbatore.

Co-Curricular Activities:

1. Participated in Faulty Induction and Training Workshop of 200 hours organized by G. H. Raisoni Academy for Human Excellence, Nagpur.

2. Member of Organizing Committee for SHIKHAR’11 –A State Level Technical Event- Organized by Jhulelal Institute of Tech.,Nagpur.

3. Participated in Summer Training for Engineering Students conducted by BSNL at RTTC Nagpur.

4. Industrial visit to Regional Remote Sensing Centre (RRSC) for Indian Space Research Organization (ISRO) at Nagpur in August 2011. Here we were shown the process of transmitting and receiving data on uplink and downlink frequency. Personal Profile:

Father’s name : Nandlal D. Patel

Date of Birth : 14th June 1990

Languages known : Marathi, English & Hindi

Nationality : Indian

Declaration:

I hereby declare that the information given above is true to the best of my knowledge & belief.

Date: / /

Place: Bengaluru Patel Suruchi Nandlal

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