Resume

ASIC Verification Engineer

Location:

India

Posted:

June 03, 2016

Contact this candidate

Resume:

Vamsi Kumar Paidi

acu2s4@r.postjobfree.com u

Career Objective

Core Competencies

Dedicated and disciplined VLSI Design and Verification professional, seeking the position of VLSI Design and ASIC Verification Engineer, to contribute to the company's growth and in turn ensuring personal growth within the organization. I believe that my technical, functional and communication skills will enable me in facing the challenging career ahead.

Verilog, SystemVerilog, VHDL, SystemVerilog Assertions, UVM

ASIC/FPGA Design Flow, Digital Design methodologies, test and checker plan development

RTL Coding, FSM based design, Simulation, Synthesis

Perforce & Code Collaborator

Code Coverage, Functional Coverage

Debugging Skills

Analytical & Interpersonal Skills

Quantitative Research and Problem-Solving Skills

Professional Experience

Verification Engineer

Perfect VIPs Techno Solutions Pvt Ltd, Bangalore

From Oct. 2013 to Present

Education

Year

Degree

Institute

University

2010-2012

M.Tech in VLSI Design

Gitam Institute of Technology,

GITAM University.

2005-2009

B.Tech. in Electronics & Communication Engg.

Saint Theressa Engineering Coleege,

JNTU kakinada, Andrapradesh.

Major Projects Handled

Industrial Experience:

Project: SATA Test-suite (IIP-VIP) Verification Environment using UVM as Verification Engineer at Avago & M-star Client. (June 2015-May -2016)

Description: Project involves Design Verification IP development of Serial ATA. This IIP can be used to verify SATA designs with purely SERDES. Basically SATA is a layered protocol, which involves Physical, Link, Transport, Command and Application layers. Physical layer is responsible for initialization of link including speed negotiation. Link layer is responsible for flow control, encoder, decoder, scrambler, CRC generator. Transport/Command/Application layer deals with FIS construction.

Skills: UVM (Universal Verification Methodology), System Verilog.

Tools: VCS

Responsibilities:

Development of test plan for Physical Layer, Transport layer, Link layer.

Added Sequences and tests according to test plan for Host DUT – Device VIP Configuration

Development of error scenarios test cases.

Developed tests for Application Layer According to the test plan in Both the Configurations.

Regression support and primary verification debug

Debugging and Reporting of failed tests in Regression

Listed out the uncovered bins and added tests to improve the Coverage Percentage

Coverage Report analysis and added additional Bins.

Wrote corner case tests.

Implemented tasks related to PHY/ Transport Layers.

Enhanced the BFM to communicate between DUT and VIP.

Enhanced command driver.

Architecture Designing and Preparing Test Cases to validate application.

Executing stimulus in different test environments. Log test results.

Achieve the functional results and Verify on the each and every block of Architecture.

Checking the coverage information. Tracing the results on scoreboard.

Process done on verification methods (UVM) Architecture verification.

Process observed corner-cases on total design in different scales on verification components.

The Achieved design functionality verified and tested by Functional verification.

Identify bugs, regression failures debug and resolve them with the help of the IIP Team

Reports to Project Lead about Status of assigned tasks.

Prototype:-

Participated in regular team meetings by Lead and Manager.

Directly interacting with SATA_TEST_IIP US team In Scheduled Meetings

Project: Verification of SATA 3.2 Environment using UVM as Verification Engineer at Synopsys Client. (Nov 2014-May -2016)

Skills: UVM (Universal Verification Methodology), System Verilog.

Tools: VCS

Description: Project involves Verification IP development of Serial ATA. This VIP can be used to verify SATA designs with SERDES. Basically SATA is a layered protocol, which involves Phy, Link, Transport, Command and Application layers. Physical layer is responsible for initialization of link including speed negotiation. Link layer is responsible for flow control, encoder, decoder, scrambler, CRC generator. Transport/Command/Application layer deals with FIS construction.

Responsibilities:

Development of test plan for Physical Layer

Added Sequences and tests according to test plan for Host VIP – Device VIP Configuration And Host DUT – Device VIP Configuration

Development of error scenarios test cases.

Developed tests for Application Layer According to the test plan in Both the Configurations.

Regression support and primary verification debug

Debugging and Reporting of failed tests in Regression

Listed out the uncovered bins And added tests to improve the Coverage Percentage

Coverage Report analysis and added additional Bins

Generation of combined coverage report from regression result.

Wrote corner case tests.

Implemented tasks related to PHY/ Transport Layers.

Enhanced the BFM to communicate between DUT and VIP.

Enhanced command driver.

Architecture Designing and Preparing Test Cases to validate application.

Executing stimulus in different test environments. Log test results.

Achieve the functional results and Verify on the each and every block of Architecture.

Checking the coverage information. Tracing the results on scoreboard.

Process done on verification methods (UVM) Architecture verification.

Process observed corner-cases on total design in different scales on verification components.

The Achieved design functionality verified and tested by Functional verification.

Identify bugs, Regression failures debug and resolve them with the help of the VIP Team

Reports to Project Lead about Status of assigned tasks.

Prototype:-

Participated in regular team meetings by Lead and Manager.

Directly interacting with SATA_TEST_VIP team In Scheduled Meetings

Project: Verification of APB 3.0 Environment using UVM as An Verification Engineer.

Description: AMBA APB is low bandwidth and low performance bus. So, the components requiring lower bandwidth like the peripheral devices such as UART, Keypad, Timer and PIO (Peripheral Input Output) devices are connected to the APB. The bridge connects the high performance AHB or ASB bus to the APB. So, for APB the bridge acts as the master and all the devices connected on the APB bus acts as the slave. So, at a time the bridge is used for communication between the high performance bus and the peripheral devices. It also be used to access the programmable control registers of the peripheral device.

Skills: UVM (Universal Verification Methodology), System Verilog.

Tools: Nc-SIM, Questa, VCS

Responsibilities:

Study of APB 3 protocol specification.

Development of test cases according to test-plan.

Creation of test-plan development and test-cases

Coverage implementation for the features to be verified

Regression support and primary verification debug

Coverage analysis and closure by adding test cases for uncovered functionality or code and by adding exclusions.

Debugging of regression failures.

Listed out the uncovered bins And added tests to improve the Coverage Percentage

Implementation of test-cases as per Cover-points.

Generation of combined coverage report from regression result.

Technical Skills