Test Cases Engineer
Resume:
NIRAV A. CHUDASAMA
***** ***** *** ******, *******, CA - 94536. Email: *.*****.*@*****.***
Contact: 408-***-**** www.linkedin.com/pub/nirav-chudasama/24/954/9bb/
SUMMARY
-Strong background in Digital Logic Design and Verification.
-Skills include Verilog, Systemverilog, PERL, Shell, C and C++.
-Experience on Constraint random verification environment with functional and code coverage.
-Knowledge of developing UVM based verification environment and tests.
-Debugging skills using Logic Analyzers and Oscilloscopes.
-Familiarity with EDA Tools for Design, Simulation and Debug.
-Experience with RTL and Gate Simulations using SDF File.
OBJECTIVE
Seeking an exciting fulltime position in ASIC/FPGA Verification and/or Validation
SKILLS
Languages : Verilog, System Verilog, SV – UVM. C, C++, PERL, Shell.
EDA Tools : Mentor Graphics Questasim, Synopsys VCS, Cadence NCsim.
Debugging Tools : Verdi, Cadence SimVision, Mentor Graphics Visualizer.
Operating Systems : Windows, Linux.
Lab Equipment : Logic Analyzer, Oscilloscope.
INDUSTRY EXPERIENCE
VeriFast Technologies, Milpitas, CA: Verification Engineer 03/01/2015 – Present
-Primary Responsibilities include UVM Testbench development, UVM Test cases generation, running regression and analysis of regressions, generate and analyze functional and code coverage data and running gate level simulations with SDF.
-Working on USB PD Block and USB Type C block in 2 projects, where we developed and enhanced the UVCs and created test cases.
-Running regressions for RTL with code coverage and gate level regressions with sdf.
Quantenna Communications, Fremont, CA: ASIC Verification Engineer 08/01/2013 – 02/28/2015
-Primary Responsibilities include testbench development, testcases generation, regressions run and analysis, functional and code coverage run and analysis, creating assertions, running gate level simulations and regressions, running gate level simulations with SDF, developing and optimizing scripts for pre and post processing.
-Worked on 802.11 PHY Baseband block on 3 projects where we developed and enhanced the testbench environment and created testcases for different sub-blocks and different scenarios.
-Worked on the digital block of 2 RFIC chip projects where I worked on testbench and testcase development. Worked on SPI Master and Slave Block for RFIC projects.
-Board level debugging for DFE of RFIC chip was done using Logic Analyzers.
-Assisted in development of constrained random verification environment with functional and code coverage and development of scripts pertaining to simulations and regressions.
-Worked on regressions and simulations with RTL and Gate level (with SDF).
-Extensively used Verdi tool for simulation debugging of failed test cases.
-Assisted in debugging and development of C++ based reference models.
Arasan Chip Systems, San Jose, CA: Design Engineering Intern 06/01/2013 – 07/31/2013
-Primary Responsibilities include Verification and Development of USB testbench environment.
-Worked on creating test cases, running regression scripts and analyzing results.
-Created infrastructure to generate Coverage reports for specific blocks.
-Worked on USB 2.0 Device verification.
VeriFast Technologies, San Jose, CA: Verification Intern 06/23/2012–05/31/2013
-Did Verification Training Program where I learned complete Fundamentals of Functional Verification, functional Coverage, Constrained Random Testing, Perl Scripting and System Verilog UVM with hands-on lab projects.
-Developed and implemented verification test case in Verilog and SystemVerilog.
-Worked on Coverage Driven Constrained Random Verification using Systemverilog.
-Developed file writing during simulation and did post simulation checking using Perl.
-Worked with a team on project USB Host Router and did verification using System Verilog.
-Worked on I2C VIP and developed sequence generator and driver in both master and slave mode.
-Worked on SPI VIP and developed monitor and checker for both master and slave mode.
-Developed testbench and test cases for AMBA AXI Protocol.
Smartec Solutions, Vadodara, India: Embedded Systems Engineer 08/01/2009 – 06/30/2010
-Worked on Embedded Systems projects using C programing and development of PCB Designs.
-Worked on ARM7 based microcontrollers as well as on 8051 microcontrollers.
-One of the projects we worked on was the Portable Media Player.
PROJECTS
USB Host Router
-Created a test bench in SystemVerilog using constrained random verification technique.
-Made verification test cases along with functional and code coverage for each test.
-Created Perl script for post simulation comparison of data.
IP Integration with AHB Core
-Design 4 IP cores in SystemVerilog, integrated using AMBA AHB Protocol.
-It has Instruction Decoder as Master-IP which provides decoded op-codes to the slaves.
-An Adder, Multiplier and Divider are Slave-IPs which fetch instruction from master.
-Used System Verilog Interface and Assertions for AMBA AHB Protocol.
Routed Network Switch
-Verilog project for Design, Simulation and Synthesis of an Ethernet network switch.
-32 I/O ports and each port have 8-bit data width and external memory for Packets storage.
-There are push in and push out signals for each port for control of packet entry and exit.
8-Bit Scalar Processor
-Verilog Project for Design, Simulation and Synthesis of an 8-bit Scalar Processor.
-It has 10 Operands, 4 control registers with a flag register.
-It does arithmetic operations like addition, multiplication and division.
EDUCATION
Masters of Science in Electrical Engineering December 2014
San Jose State University, San Jose, CA.
Bachelors of Engineering in Electronics & Communications Engineering May 2009
Gujarat University, Gujarat, India.
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