Vlsi physical design

LEELA SRAVANTHI .P

Email Id: **************@*****.*** Phone: +91-955*******

Seeking a challenging and enduring job in professional organization where my skills and abilities could be fully utilized to achieve organizational goals and professional growth.

Experience:

Physical Design Trainee, Institute of Silicon Systems, Hyderabad,

June 2013 – April 2014.

Assistant Professor, RVR institute of engineering and tech, Hyderabad

May 2011-Aug 2013

Technical Exposure

Programming Languages : Verilog HDL.

Frontend Synthesis Tools : Cadence RTL Compiler

Backend Tools : Cadence SOC Encounter, Cadence ETS, Cadence Virtuoso,

Verilog Simulation : VCS

Scripting Languages : TCL, Shell

Education:

M.Tech (Electronics and Communication Engineering) [2009-11] with 84 % aggregate

B.Tech (Electronics and Communication Engineering) [2003-07] with 69.5 % aggregate.

Inter(MPC) [2001-2003] with 74%

SSC[2001] with 72%.

Project Details:

Project#1 : PCI DATA

Project Type : Top Level

Objective : Timing Driven Layout

Tool : SOC Encounter, ETS

Technology : UMC 0.18micron, 5 Metal Layers

Macros/STD Cells : 12/24461

Gate Count/Area :1,28,920/1572423.4 um^2

Clocks : 8 Clocks, Max 150 MHz

Role : Die size, PG planning, Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trial Route, Power Analysis, RC Extract, Timing analysis, IPO, CTS, Detailed routing.

Project#2 : (Block Level)

Project Type : Block Level

Objective : Timing Driven Layout

Tool : SOC Encounter,ETS

Technology : TSMC 0.18micron, 5 Metal Layers

Macros/STD Cells : 12/27061

Gate Count/Area :3,03,884/1547443.2 um^2

Clocks : 17 Clocks, Max 200 MHz

Role : Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trial Route, Power Analysis, RC Extract, Timing analysis, IPO, CTS, Detailed routing

BRX_TOP (Block level):

Objective : Timing Driven Layout

Tools : SOC Encounter, ETS.

Gate count : 11000

No. of Clocks : 3

Frequency : 150MHz

Technology/Layers : TSMC 0.18 micron/5 Metal Layer

Role : Performing sanity check, Design import, Floor Plan, Power Plan,

Placement, Trial Route, Power Analysis, RC Extract, Timing analysis, IPO, CTS Adding Filler cells.

Logic synthesis:

Tools : RTL Compiler

No of clocks : 2

Frequency : 200MHz

Role : Prepared Constraint file, TCL file, Performed Wire load and Zero Wire load Model Timing Checks.

Standard Cells Layout Designing:

Tools : Virtuoso Layout Editor, Assura Verification.

Design : Layout of a CMOS gates.

Role : Drawing the stick diagram from spice net list, drawing layout and verifying DRC and LVS.

Personal Details:

Date of Birth : 22-9-1986

Marital Status : married

Address : Vanasthalipuram,hyderabad

Phone : +91-955*******

Hobbies : Watching Movies and Listening Music.

Declaration:

I hereby declare that the above written particulars are true to the best of my knowledge and belief.

DATE:

sravanthi

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