SHEMAK KODAJE

*** ******** *** *** * Syracuse NY 13210 Mobile: 315-***-****

Email: actzvj@r.postjobfree.com LinkedIn: http://www.linkedin.com/in/shemakkodaje EDUCATION

Master of Science – Electrical Engineering May 2016 Syracuse University, L.C Smith School of Engineering and Computer Science- Syracuse, NY GPA 3.56 Relevant Coursework: Computer Architecture, VLSI Testing and Verification, VLSI Design Methods, VLSI Static timing Analysis, Digital Machines and Design, Analog Circuits, Digital Communication Bachelor of Engineering - Electronics and Communication June 2014 People’s Education Society Institute of Technology (PESIT), Bangalore, India GPA 3.7 Relevant Coursework: VLSI Design, Microcontrollers, Microprocessors, DSP, Computer Programming TECHNICAL SKILLS

Programming: VHDL, Verilog, C, C++, Perl, Assembly language(x86)

Proficiencies: RTL verification, Formal verification, Gate level Simulation, Hardware Descriptive Language

Tools: Xilinx ISE, Modelsim, Cadence Incisive HSPICE, Cadence Virtuoso, MS Visual Studio, Matlab, Simulink

Operating Systems: UNIX, Windows

PROFESSIONAL EXPERIENCE

General Electric (GE), R&D Intern Jan 2014 – June 2014

Spearheaded the development of a test-bench to automate the end-to-end communication process in a Locomotive and automated the manual testing using C

Successfully managed and Co-ordinated with teams to design the test-bench as per the company’s requirement

Received appreciation from Project manager for my diligent contribution in writing scripts using C ACADEMIC PROJECTS

Hardware Circuit Timing Analysis Aug 2015 – Dec 2015

Implemented Elmore delay technique to calculate the interconnecting delays in a hardware circuit

Incorporated the buffer insertion technique to insert buffers at a point where there is a large load (fan out point) to overcome the circuit delay and distribute the load

Worked on the retiming of circuit so as to decrease the clock period and to increase the speed of the circuit

C++ program implementation to reduce the overall circuit delay by gate sizing with the use of lagrangian technique Dynamic Branch Prediction Using Perceptrons in C++ Aug 2015 – Dec 2015

Simulated the results using simple scalar simulator in C++ to analyze the performance of perceptron predictor

Aimed at reducing branch miss-prediction rate and increasing instructions per cycle Designed a 8-bit Micro Processor in 90-nm CMOS technology: Aug 2014– Dec 2014

Constructed schematics for each part of the circuits with Cadence, analyzed key parameters including the delay, the frequency and the sizing with preliminary W and L values.

Made simulation to tune a considerable sizing. Finished the layout of each part of the processor.

Implemented the whole layout in Virtuoso with DRC, LVS clean Design of a Built-in-self-test (BIST) circuit: Jan 2015 – May 2015

Micro-architected and designed a BIST controller, an Arithmetic Unit, a Test Pattern Generator and an Output Response Analyzer.

Implemented a Pseudo random pattern generator (PRPG) to perform the test pattern generation and a multiple- input signature register (MISR) for the output response analyzer ACHIEVEMENT:

Presented a Paper on National Level Paper Presentation Competition held at BITS Pilani, India on the Topic

“ELECTRIC AIR GUITAR” which secured 3rd place held on February 3rd 2013

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