Verilog,ASIC,SOC,FPGA,VHDL,PERL

RIKTA SARMA

E-mail: **********@*****.**

Siva Sai PG,#17&18

Mobile: +91-974*******

Raghavendra Layout,1st cross

Behind Yashomati Hospital

Marathahalli,Bengaluru-560037

CAREER OBJECTIVE:

To work in a challenging environment of VLSI which will help me to

improve my technical skills while contributing to the growth of the

organization.

EXPERIENCE: Working as a Project Trainee at CDAC, Bengaluru from 28th

December 2015 to May 2016.

Title: Hardware implementation of building blocks of AMBA AXI4.0 on FPGA.

Tools/Language Used: Verilog HDL, Modelsim6.3g,Xilinx ISE Design suite

14.4.

Summary: The verilog codes for the five different channels of AMBA AXI4.0

are written.The top -level module will be a controller fsm which specifies

whether write or read transaction is taking place.Burst transactions are

also carried out.Then it will be implemented on VIrtex-6 FPGA.

ACADEMIC PROFILE:

Qualification Institution Passing Aggregate(%/CGPA)

Year

M. Tech (VLSI VIT University, Vellore 2016 8.77 (till 3rd

Design) semester)

B.E. (Electronics Assam Engineering 2013 79.7

& College

Telecommunication)

AISSCE (12th) Kendriya Vidyalaya 2008 85.6

H.S.L.C (10th) Saint Mary's English 2006 85.2

High School

TECHNICAL SKILLS:

Programming Languages Verilog HDL, VHDL, Basics Of C and C++.

Scripting Languages Perl, TCL.

Layout, Simulation and RTL to GDS-II using SOC Encounter, Virtuoso,

Circuit Design Softwares RTL Compiler, Quartus(Altera),

ModelSim-Altera 6.5b, Modelsim SE-EE 5.4a,

Atlanta M 2.0.

ACADEMIC PROJECTS UNDERTAKEN

1. High performance energy efficient building block(Adder) of

ALU.(Published in Springer)

Tool used : Cadence Virtuoso Tool.

Project Description: Adders can be implemented using EX-OR/EX-XNOR

gates, transmission gates, HSD(High Speed Domino)technique, domino logic,

Parallel Feedback Carry Adder. In the circuit developed, there is less

voltage degradation, no glitches, less power consumption than the

conventional PFCA adder circuit.

2. Implementation of UART on ASIC platform.

Tools Used : ModelSim 6.5b,NC Launch, RTL compiler, Cadence Encounter.

Project Description: In this project, UART using the Verilog as the

preferred HDL language is implemented.The sub-level modules are verified

using SOC encounter tool(for physical synthesis) with logic synthesis

using RTL Compiler. Floor planning, Placement, Routing using SoC

Encounter tool are done to get the GDS-II file..

3. Design and analysis of low noise amplifier using FinFETs.

Tool Used : Cadence Virtuoso Tool..

Project Description: This project concentrates on developing and

analysis of a major topology in LNA ie Common gate LNA configuration

using 30 nm BSIM-CMG model.

4. To design a 4 way traffic light controller and a 8 way traffic light

controller.(B.E)

Tool Used : Modelsim SE-EE 5.4a tool.

Project Description: In this project three coloured LEDs

(red,blue,green) are used to specify the traffic signals. The VHDL codes

for both the TLCs are written and then implemented in spartan3 hardware.

PROFESSIONAL CERTIFICATION :

1. Undergone summer training (4 weeks) on VHDL at CETPA InfoTech Ltd,

Noida.

CO-CURRICULAR ACTIVITIES:

Workshops attended Attended a two-day workshop on VLSI using FPGA.

Seminar Delivered Static Timing Analysis (STA) at VIT

University-Vellore.

Paper Presentation Presented a paper on "Design Of Basic Building Block

Of ALU" in Springer International Conference on Soft

Computing Systems held at Noorul Islam University at

Kumaracoil, Kanyakumari District.

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