FPGA desgin

Yuxin Wen **** e **TH street, Brooklyn, NY, *****

Phone number: 917-***-**** E-mail: ******@***.*** Education

New York University, New York, NY May, 2015

Master of Science in computer engineering (GPA 3.42/4.0)

Nanjing University of Aeronautics & Astronautics (NUAA), Nanjing, Jiangsu, China June, 2013 Bachelor of Engineering in Testing and Control Technologies Instrument Coursework

Advanced Hardware Design Ultra-low Power Bioelectronics Introduction to VLSI Design Computer Architecture Real-time Embedded Systems VLSI System and Architecture Design Reconfigurable System Design Electronic Power Supplies VLSI Testing and Security Skills

Language: VHDL, Verilog,C, C++, Matlab, Assembly Language Software: Modelsim, Xilinx ISE Design Suite, Altera Quartus II, Cadence, Altium Designer Work Experience

Flying Leopard Company Affiliated to China’s First Aircraft Design and Research Institute August, 2012 Assistant Engineer

Hardware wire connection, newly made parts calibration with other technology workers

Hardware circuit’s simulation in Altium Designer in the laboratory. Xian Feibao Development Company July, 2011

Manager Assistant

Communication with the subordinates of manager,

Helping manager verify materials from the other departments. Academic Projects

FPGA-Based SPWM Generator for High Switching Frequency DC/AC Inverters June, 2015

Design of a DC/AC inverter switch controller with a frequency of 100 MHz using VHDL

Implement and performance optimizing on FPGA board Xilinx Spartan-6 FPGA-Based Traffic light Design April, 2015

Design a traffic light with timer function and real-time function in Verilog code

Implement on Xilinx Spartan-6 FPGA board

Two Channel EEG Amplifier Design on PCB board December, 2014

A fully-functional, 2-channel wireless scalp EEG system with one right leg drive channel

Fully working PCB design with Altium Designer, manually soldered and tested FPGA-Based AES Encryption & Decryption System Design November, 2014

Design of a data transform system using Rijndael algorithm

Adding timing constraint for optimizing performance and generating timing & power report

Implement on Xilinx Spartan-6 FPGA board and test with provided IP core ChipScope Power Analysis of Matrix Multiplication May, 2014

Design of BRAM, memory controller and matrix multiplication using VHDL code

Analyzing the power in different matrix size with Cadence Embedded Timer and Counter Design May, 2014

Embedded counter incrementing when state of button changes from released to pressed state

Embedded timer recording the time duration between button press and release

Implement on STM32 Development Board using C language with timer accurate of 0.01s 4-bit fixed-point ALU design December, 2013

Design and simulation of a 4-bit fixed-point ALU in TSMC 0.25μm CMOS process with Cadence

Arithmetic and logic functions including rotate and shift with clock frequency of 100 MHz

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