Currently i am doing my M.Tech by research in NITK

RESUME

Name: N.Sridhar Reddy

Email: ***************@*****.***

Mobile: +91-990*******

EDUCATIONAL QUALIFICATIONS:

LEVEL

OF

EDUCATION

INSTITUTION

BOARD/UNIVERTY

YEAR

OF

PASSING

AGGREGATE

(in %)

M.Tech by

Research

(VLSI Design)

National institute of

technology,

Karnataka

National institute of

technology, Karnataka

2016 7.0 (CGPA)

B.Tech

(Electronics &

Communication

engineering)

Hyderabad institute of

technology and

management

Jawaharlal Nehru

Technological

University, Hyderabad

2013

70.06

Intermediate

(Science+Maths

stream)

Sri chaitanya junior

kalasala

Board of Intermediate

Education, A.P

2009

84.8

S.S.C

Satya sai vidyaniketan

high school

Board of Secondary

Education, A.P

2007

88.83

Academic Projects:

B.Tech project:

1. Implemented an IEEE paper on low-power design technique for flash A/D converters based on reduction of the number of comparators using CADENCE in UMC 350nm CMOS technology.

Address for communication:

Room no-239, V-hostel block,

NITK,Surathkal,

P.O.Srinivasnagar, Dakshina

kannada (District), Karnataka-

575025

CAREER OBJECTIVE:

To secure a challenging position in my field of study where i can effectively contribute my skills.

M.Tech by Research projects:

Major Projects:

1. I have designed a Low-Power Area-Efficient Dual Channel SAR ADC Using Common Capacitor Array technique in UMC 180nm CMOS technology using CADENCE tool under the guidance of Dr.M.S.Bhat. To achieve area efficiency, a common Capacitor Array (CA) technique is proposed wherein we use only N+1 CAs instead of 2N for N-channels in a differential architecture. (This architecture is completely new in the literature and a conference paper is sent for the publication).

Applications: Multichannel neural recorders and CMOS image sensors. Specifications of one single channel: Technology= 180nm, Resolution= 7, Sampling Frequency (MS/s)= 4, SNDR= 42.46dB, SNR= 43.30dB, SFDR= 52.99dB, ENOB= 6.76, Power (µW)= 43.85, FOM (fJ/conversion-step)= 101.14, (All the above parameters are calculated at nyquist frequency) DNL/INL (LSB)= -0.27/0.33. Total capacitance used for 7-bit differential DAC: 500fF. 2. Currently i am working on design of 0.5V Flash ADC with reduced number of comparators using CADENCE in UMC 90nm CMOS technology. It requires only half of the comparators compared to conventional Flash ADC. Number of comparators can be reduced further by using interpolation technique. (i.e., upto 75% of the total comparators can be eliminated by both the techniques).

Mini projects:

1. I have designed a Trans conductance-C (Gm-C) bi-quad low pass Butterworth filter in 350nm CMOS technology node from TSMC using LTSpice circuit simulator. 2. Layout of universal shift register was done in magic and spice parameters were extracted using IRSIM.

3. Direct cache memory is implemented using Verilog HDL. TECHNICAL SKILLS:

Programming languages known: C, Verilog HDL, Perl.

Tools: Cadence, Magic, Ngspice, Irsim, Ltspice.

Personal Profile:

Name : N.Sridhar Reddy

Fathers name : N.V.Ramana Reddy

D.O.B : 01-07-1991

Nationality : Indian

Languages : Telugu, Hindi and English

Hobbies : Playing cricket, Jogging.

Declaration:

I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for the incorrectness of the above mentioned particulars. Date: N.Sridhar Reddy

Contact this candidate