M.Tech(Iiit,Delhi)/Vlsi/Embedded/Intern/St Microelectronics

Education

Indraprastha Institute of Information Technology, Delhi

M.Tech(ECE)

**** – Present

CGPA: 7.4

Guru Tegh Bahadur Institute Of Technology, Delhi

B.tech(ECE)

**** – 2014

Percentage:80.82%

D.L.D.A.V Model School, Delhi

CBSE(Class XIIth)

2009 – 2010

D.L.D.A.V Model School, Delhi

CBSE(Class Xth)

2007-2008

Percentage:88.4%

Percentage:90%

Skills

Expertise Area Digital Electronics, Network on Chip, Embedded Systems Programming

Language

C,C++,Verilog HDL, Bluespec System Verilog, TCL

Tools and

Technologies

Cadence Virtuoso Schematic, Primetime, Primetime GCA, Synopsys Design Compiler, MATLAB, Cadence Encounter and Innovus, Xilinx IDE Technical

Electives

Analog CMOS Design, Digital VLSI Design, System on Chip Design and Testing, Advanced Embedded System, Memory Design and Testing, VLSI Design

Internship

JASMINE KAUR GULATI

Email: *****************@*****.***

DOB: August 06, 1992

Address: E-105, Shastri Nagar, Delhi-110052

Mobile No. +919*********

ST Microelectronics, Greater Noida

Guide: Mr. Bhanu Prakash(ST Microelectronics)

Area Reduction of a digital design addressing industry dominant challenges which include Floorplanning, Clock tree synthesis and signal integrity issues.

Aug,15–Jun,16

Laser Science and Technology Centre, DRDO (Research) Guide: Mr. Satya Prakash(Scientist F )

Study and design of Laser based Frequency transmitter and receiver using Atmega 16 microcontroller.

Jun,13–Aug,13

Laser Science and Technology Centre, DRDO (Research) Guide: Mr.Manish Borkar(Scientist – E )

Study of data acquisition and control system of a laser based system. Jun,12–Aug,12

Projects

Design of Lift Controller system for most optimized lift movement.

Controller system for two interconnected lifts is designed for a 10 floor building using efficient lift movement algorithm.

May,15 – Jun,15

Team Size-3

Design of 6T and 7T SRAM cell in Cadence and study their operation in sub-threshold region

SRAM cell are designed in cadence and figure of merits: read margin and write margin are studied and compared them with the memory cell in sub-threshold region.

May,15 – Jun,15

Team Size-3

Prototyping of Network on Chip on FPGA

Guide: Dr. Sujay Deb

Study of NoC architecture and its synthesis and implementation on Virtex-5.

Jan,15 – Apr,15

Team Size-2

Design of ALU with pipeline stages in Bluespec and implementing on Spartan-6 FPGA Board

Guide: Dr. Alexander Fell

ALU unit is designed using Bluespec system Verilog with four pipeline stages and implemented on FPGA board.

Mar,15 – Apr,15

Team Size-2

NOC Router implementation for concurrency in real time and general purpose traffic

Guide: Dr. Sujay Deb

Design of a router “Hard Real-time Aware Interconnect Network Router” (HRES) and compare its area, power demands, and throughput and latency response with that of a normal virtual channel router Aug,14 – Nov,14

Team Size-3

Intelligent Street Lighting System

Guide: Mr. Narang Kishor

Design a flexible as well as power saving street lighting system using sensors, arm microcontroller with wireless connectivity. Design of 32-Bit MAC Unit using Xilinx on FPGA

Guide: Dr. Amrik Singh

MAC Unit designed using Verilog based on modified Booth algorithm and comparing the performance with three adder mechanisms and implementing on the SPARTAN-3 FPGA board.

Aug,14 – Nov,14

Team Size-3

Jan,14 – May,14

Team Size-4

Design of Antenna using thin wire as a substrate in HFSS Guide: Ms. Parul Dawar

A Single Patch Rectangular Micro strip Antenna was designed and simulated in HFSS.

Aug,13 – Dec,13

Team Size-4

Positions of Responsibility

Teaching Assistant at IIIT, Delhi Jan,15 – Apr,15

Teaching Assistant at IIIT, Delhi Aug,14 – Nov,15

Coordinator of various technical events in college during graduation.

Aug,10 – Mar,14

Campus Ambassador for the DTU Technical fest Renaissance. Feb,13

Event Manager for the Sports meets in the college during graduation.

Mar,12

Awards and Achievements

Got 2nd prize in technical paper presentation held in Under-graduate College, 2013.

Got 3rd position in poster making competition held at Indira Gandhi Institute of Technology, 2013.

Got 2nd rank in class 12th in school, 2010.

Participated in INDIAN SCHOLARSHIP EXAMINATION at all India level in 2009.

Secured 8th state rank in the International Informatics Olympiad, 2008.

Got Maharaja Agrasen Scholar award for class 10th, 2008. Interests and Hobbies

Academic : Solid state devices, Network on Chip, SRAM design

Interacting with new people and gaining knowledge.

Travelling and exploring the nature.

Declaration: The above information is correct to the best of my knowledge. Jasmine Kaur Gulati

Date: March 14, 2016

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