Analog/Mixed Signal Design, RF circuit Design

SOMANGSHU BAGCHI

*** ***** *** *****, *********, Texas 76013

682-***-**** ************@*****.***

Education:

University of Texas at Arlington, TX Expected May 2016

Master of Science in Electrical Engineering GPA: 3.33/4.

WBUT, Kolkata, India July 2011

Bachelor of Technology in Electronics & Communication Engineering

GPA: (8.27/10.0), Junior/Senior GPA (8.38/10)

Coursework:

Low Noise Electronics, Analog CMOS IC Design, Digital VLSI Design, Advanced Electronics, Embedded Microcontroller Systems,, Semiconductor Device Theory, Foundations in Semiconductor,, Introduction to MEMS and Devices, Wireless Communications Systems, Wireless Systems Propagation and Modelling, Information Theory and Coding, Linear Systems Engineering

Technical Skills:

Hardware Design Language: VHDL, SystemVerilog, Embedded C

Software Programming Language: C, C++, Java, DB2, HTML, Python, COBOL

Tools: Agilent ADS, Code Composer Studio, Kiel, Xilinx Design

Suite, MatLab, Cadence Virtuoso Schematic and Layout

Editor, ICFB, HSpice, ORCAD PSPICE 16.6 Lite, LTSpice,

Hercules

Additional: Knowledge in low power CMOS design, Phase Locked Loop,

VCO, LDO, LNA and all possible concepts for Analog IC design

Platforms: Windows, Linux

Database: Oracle, SQL Server

Others: Microsoft tools MS Office Word, MS Powerpoint, MS Excel,

Troubleshooting software, fix computer hardware parts

Academic Projects:

Design of a Low Noise Operational Amplifier with Output Buffer

Designed 2-stage OpAmp with Miller and Lead Compensation with output buffer to drive 1 KΩ

resistive load. Achieved GBW of 40 MHz, Gain of 96 dB, phase Margin of 75 degree and Input

Referred noise of 82.57nV/sqrt(Hz) at 10 Hz; CMRR:67 dB,power dissipation<0.3 mW;tsmc 180nm

process.

Design of Telescopic Cascode Differential Amplifier

Designed and simulated the schematic with a load of 1pF at the output with a tail current less than 40uA. Achieved GBW of 50.57 MHz, DC Gain of 65.67 dB, Phase Margin of 68.1 degree and Slew Rate of 33.3 V/us.

Design of Symmetric Operational Transconductance Amplifier

Designed and simulated the schematic with common source buffer with power dissipation below 1.6 mW. Implemented the layout using common centroid and inter digitization techniques.

Achieved GBW of 65.39 MHz, DC Gain of 113.1 dB, Phase Margin of 73.6 degree, Slew Rate of 40.4 V/us and input referred thermal noise of 7.274 nV/sqrt (Hz).

Design of Fully Differential Two Stage Amplifier with Common Mode Feedback

Tested a two stage differential operational amplifier, which met all the design specifications. From Slew rate specifications, current at each stage was determined. After preliminary design was simulated, sizes of the transistors are modified to ensure proper CMFB bandwidth, enough phase margins, and enough differential gain, differential bandwidth.

8 bit Modulo Adder Design

Designed the 8 bit adder in 32nm Synopsys PDK with minimum EDP of 74.35 pJ.ps and maximum frequency of 1.919 GHz using cadence Virtuoso, Synopsys Hspice, Hercules, StarRC. Designed the Adder cells using pass-transistor logic to achieve minimum area of 159.43 sq. micron.

Design and Analysis of Nine staged CMOS Ring Oscillator using 45nm technology

Used Cadence virtuoso environment to design the oscillator and the various performance parameters like noise, delay, glitches etc. were analyzed and reduced accordingly to optimize the efficiency of the nine stages ring oscillator

Precise Cable and Antenna Measurements, Interference Analysis in the Field Using FieldFox handheld vector network analyzer

Low Frequency Signal Generator and Scalar Network Analyzer using ARM M4F core based microcontroller (TM4C123GH6PMI microcontroller)

Designed a system capable of capturing analog signals and generating various waveforms. This project has a command line interface (TeraTerm) capable of controlling the system and providing measurement data back to the user. Additional capabilities allowed output impedance correction, scalar network analysis, and simple voltmeter operations.

Rate versus Power Control in IS-95, CDMA-2000 and LTE

Analysis of Quality of Service (QoS) for IS-95 and CDMA 2000 standards by comparing their Rate

and Power control using Channel Inversion power control, Equal Gain Allocation and Waterfilling

Power control schemes using MATLAB for SISO, SIMO, MISO and MIMO with variable Doppler

shift

Molecular Transistor and its Challenges (Term Paper)

My paper reviewed one of the most challenging aspect in integrated circuit design, ‘the designing of molecular transistor for high-density memory applications’.

SMS Based Automation using 8051 microcontroller(Corefuture, Kolkata)

Work Experience:

Tata Consultancy Services Ltd Kolkata (India)

Systems Engineer

IT experience in delivering Service Management solutions in the domain of Banking and Finance Services.

Joined as a Trainee and received two successive promotions based on performance which resulted in securing a

Systems Engineer position

Client Details: Citibank, USA April, 2013- June, 2014

Citibank MAT (Mortgage assistant Tool) Development Program:

Was involved in the development of a loan selection tool called MAT (Mortgage assistance tool) with the use of JAVA, Spring Architecture on J2EE Eclipse platform and also using PLSQL. The application would analyze all the entered information by the user and suggest the best possible loan options to them.

Client Details: Experian, United Kingdom May, 2012- Feb., 2013

Acted as a technical support personnel in maintaining and monitoring the applications

Worked on Oracle Image Processing applications and image-enablement solutions

Worked on the assignments of HTML, JavaScript and Java and gained valuable exposure

The various roles involved analysis of customer requirement preparing the design, programming and providing support to business customers and constantly maintaining 100 percent store credit for customer satisfaction

Provided post-implementation maintenance support for application and prepared daily project report on Excel spreadsheets based on applications

Additional Information:

Was awarded the State Merit Scholarship based on the result of the Higher Secondary Board Examination conducted by WBCHSE

Was awarded with TCS gems for the best team performance

Worked as a sales associate at Follett Corporation, UTA Bookstore

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